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Marc Zyngieroupton
Marc Zyngier
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oupton
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arm64: sysreg: Add layout for ICH_VTR_EL2
The ICH_VTR_EL2-related macros are missing a number of config bits that we are about to handle. Take this opportunity to fully describe the layout of that register as part of the automatic generation infrastructure. This results in a bit of churn to repaint constants that are now generated with a different format. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20250225172930.1850838-3-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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-39
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5 files changed

+25
-39
lines changed

‎arch/arm64/include/asm/sysreg.h‎

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -562,7 +562,6 @@
562562

563563
#define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
564564
#define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
565-
#define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
566565
#define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
567566
#define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
568567
#define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
@@ -1022,18 +1021,6 @@
10221021
#define ICH_VMCR_ENG1_SHIFT 1
10231022
#define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
10241023

1025-
/* ICH_VTR_EL2 bit definitions */
1026-
#define ICH_VTR_PRI_BITS_SHIFT 29
1027-
#define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
1028-
#define ICH_VTR_ID_BITS_SHIFT 23
1029-
#define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
1030-
#define ICH_VTR_SEIS_SHIFT 22
1031-
#define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
1032-
#define ICH_VTR_A3V_SHIFT 21
1033-
#define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
1034-
#define ICH_VTR_TDS_SHIFT 19
1035-
#define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT)
1036-
10371024
/*
10381025
* Permission Indirection Extension (PIE) permission encodings.
10391026
* Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).

‎arch/arm64/kvm/vgic-sys-reg-v3.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -35,12 +35,12 @@ static int set_gic_ctlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
3535

3636
vgic_v3_cpu->num_id_bits = host_id_bits;
3737

38-
host_seis = FIELD_GET(ICH_VTR_SEIS_MASK, kvm_vgic_global_state.ich_vtr_el2);
38+
host_seis = FIELD_GET(ICH_VTR_EL2_SEIS, kvm_vgic_global_state.ich_vtr_el2);
3939
seis = FIELD_GET(ICC_CTLR_EL1_SEIS_MASK, val);
4040
if (host_seis != seis)
4141
return -EINVAL;
4242

43-
host_a3v = FIELD_GET(ICH_VTR_A3V_MASK, kvm_vgic_global_state.ich_vtr_el2);
43+
host_a3v = FIELD_GET(ICH_VTR_EL2_A3V, kvm_vgic_global_state.ich_vtr_el2);
4444
a3v = FIELD_GET(ICC_CTLR_EL1_A3V_MASK, val);
4545
if (host_a3v != a3v)
4646
return -EINVAL;
@@ -68,10 +68,10 @@ static int get_gic_ctlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
6868
val |= FIELD_PREP(ICC_CTLR_EL1_PRI_BITS_MASK, vgic_v3_cpu->num_pri_bits - 1);
6969
val |= FIELD_PREP(ICC_CTLR_EL1_ID_BITS_MASK, vgic_v3_cpu->num_id_bits);
7070
val |= FIELD_PREP(ICC_CTLR_EL1_SEIS_MASK,
71-
FIELD_GET(ICH_VTR_SEIS_MASK,
71+
FIELD_GET(ICH_VTR_EL2_SEIS,
7272
kvm_vgic_global_state.ich_vtr_el2));
7373
val |= FIELD_PREP(ICC_CTLR_EL1_A3V_MASK,
74-
FIELD_GET(ICH_VTR_A3V_MASK, kvm_vgic_global_state.ich_vtr_el2));
74+
FIELD_GET(ICH_VTR_EL2_A3V, kvm_vgic_global_state.ich_vtr_el2));
7575
/*
7676
* The VMCR.CTLR value is in ICC_CTLR_EL1 layout.
7777
* Extract it directly using ICC_CTLR_EL1 reg definitions.

‎arch/arm64/kvm/vgic/vgic-v3.c‎

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -284,12 +284,10 @@ void vgic_v3_enable(struct kvm_vcpu *vcpu)
284284
vgic_v3->vgic_sre = 0;
285285
}
286286

287-
vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 &
288-
ICH_VTR_ID_BITS_MASK) >>
289-
ICH_VTR_ID_BITS_SHIFT;
290-
vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 &
291-
ICH_VTR_PRI_BITS_MASK) >>
292-
ICH_VTR_PRI_BITS_SHIFT) + 1;
287+
vcpu->arch.vgic_cpu.num_id_bits = FIELD_GET(ICH_VTR_EL2_IDbits,
288+
kvm_vgic_global_state.ich_vtr_el2);
289+
vcpu->arch.vgic_cpu.num_pri_bits = FIELD_GET(ICH_VTR_EL2_PRIbits,
290+
kvm_vgic_global_state.ich_vtr_el2) + 1;
293291

294292
/* Get the show on the road... */
295293
vgic_v3->vgic_hcr = ICH_HCR_EL2_En;
@@ -633,7 +631,7 @@ static const struct midr_range broken_seis[] = {
633631

634632
static bool vgic_v3_broken_seis(void)
635633
{
636-
return ((kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_SEIS_MASK) &&
634+
return ((kvm_vgic_global_state.ich_vtr_el2 & ICH_VTR_EL2_SEIS) &&
637635
is_midr_in_range_list(read_cpuid_id(), broken_seis));
638636
}
639637

@@ -707,10 +705,10 @@ int vgic_v3_probe(const struct gic_kvm_info *info)
707705
if (vgic_v3_broken_seis()) {
708706
kvm_info("GICv3 with broken locally generated SEI\n");
709707

710-
kvm_vgic_global_state.ich_vtr_el2 &= ~ICH_VTR_SEIS_MASK;
708+
kvm_vgic_global_state.ich_vtr_el2 &= ~ICH_VTR_EL2_SEIS;
711709
group0_trap = true;
712710
group1_trap = true;
713-
if (ich_vtr_el2 & ICH_VTR_TDS_MASK)
711+
if (ich_vtr_el2 & ICH_VTR_EL2_TDS)
714712
dir_trap = true;
715713
else
716714
common_trap = true;

‎arch/arm64/tools/sysreg‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3057,6 +3057,20 @@ Field 1 UIE
30573057
Field 0 En
30583058
EndSysreg
30593059

3060+
Sysreg ICH_VTR_EL2 3 4 12 11 1
3061+
Res0 63:32
3062+
Field 31:29 PRIbits
3063+
Field 28:26 PREbits
3064+
Field 25:23 IDbits
3065+
Field 22 SEIS
3066+
Field 21 A3V
3067+
Field 20 nV4
3068+
Field 19 TDS
3069+
Field 18 DVIM
3070+
Res0 17:5
3071+
Field 4:0 ListRegs
3072+
EndSysreg
3073+
30603074
Sysreg CONTEXTIDR_EL2 3 4 13 0 1
30613075
Fields CONTEXTIDR_ELx
30623076
EndSysreg

‎tools/arch/arm64/include/asm/sysreg.h‎

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -558,7 +558,6 @@
558558

559559
#define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
560560
#define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
561-
#define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
562561
#define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
563562
#define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
564563
#define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
@@ -1018,18 +1017,6 @@
10181017
#define ICH_VMCR_ENG1_SHIFT 1
10191018
#define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
10201019

1021-
/* ICH_VTR_EL2 bit definitions */
1022-
#define ICH_VTR_PRI_BITS_SHIFT 29
1023-
#define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
1024-
#define ICH_VTR_ID_BITS_SHIFT 23
1025-
#define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
1026-
#define ICH_VTR_SEIS_SHIFT 22
1027-
#define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
1028-
#define ICH_VTR_A3V_SHIFT 21
1029-
#define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
1030-
#define ICH_VTR_TDS_SHIFT 19
1031-
#define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT)
1032-
10331020
/*
10341021
* Permission Indirection Extension (PIE) permission encodings.
10351022
* Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).

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