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Merge tag 'loongarch-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
Pull LoongArch updates from Huacai Chen: - support PREEMPT_DYNAMIC with static keys - relax memory ordering for atomic operations - support BPF CPU v4 instructions for LoongArch - some build and runtime warning fixes * tag 'loongarch-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson: selftests/bpf: Enable cpu v4 tests for LoongArch LoongArch: BPF: Support signed mod instructions LoongArch: BPF: Support signed div instructions LoongArch: BPF: Support 32-bit offset jmp instructions LoongArch: BPF: Support unconditional bswap instructions LoongArch: BPF: Support sign-extension mov instructions LoongArch: BPF: Support sign-extension load instructions LoongArch: Add more instruction opcodes and emit_* helpers LoongArch/smp: Call rcutree_report_cpu_starting() earlier LoongArch: Relax memory ordering for atomic operations LoongArch: Mark __percpu functions as always inline LoongArch: Disable module from accessing external data directly LoongArch: Support PREEMPT_DYNAMIC with static keys
2 parents 5dd2020 + 1d375d6 commit 4eeee66

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13 files changed

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lines changed

13 files changed

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lines changed

‎arch/loongarch/Kconfig‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -136,6 +136,7 @@ config LOONGARCH
136136
select HAVE_PERF_EVENTS
137137
select HAVE_PERF_REGS
138138
select HAVE_PERF_USER_STACK_DUMP
139+
select HAVE_PREEMPT_DYNAMIC_KEY
139140
select HAVE_REGS_AND_STACK_ACCESS_API
140141
select HAVE_RETHOOK
141142
select HAVE_RSEQ

‎arch/loongarch/Makefile‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,8 @@ LDFLAGS_vmlinux += -static -n -nostdlib
6868
ifdef CONFIG_AS_HAS_EXPLICIT_RELOCS
6969
cflags-y += $(call cc-option,-mexplicit-relocs)
7070
KBUILD_CFLAGS_KERNEL += $(call cc-option,-mdirect-extern-access)
71+
KBUILD_AFLAGS_MODULE += $(call cc-option,-fno-direct-access-external-data)
72+
KBUILD_CFLAGS_MODULE += $(call cc-option,-fno-direct-access-external-data)
7173
KBUILD_AFLAGS_MODULE += $(call cc-option,-mno-relax) $(call cc-option,-Wa$(comma)-mno-relax)
7274
KBUILD_CFLAGS_MODULE += $(call cc-option,-mno-relax) $(call cc-option,-Wa$(comma)-mno-relax)
7375
else

‎arch/loongarch/include/asm/atomic.h‎

Lines changed: 68 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -36,33 +36,33 @@
3636
static inline void arch_atomic_##op(int i, atomic_t *v) \
3737
{ \
3838
__asm__ __volatile__( \
39-
"am"#asm_op"_db.w" " $zero, %1, %0 \n" \
39+
"am"#asm_op".w" " $zero, %1, %0 \n" \
4040
: "+ZB" (v->counter) \
4141
: "r" (I) \
4242
: "memory"); \
4343
}
4444

45-
#define ATOMIC_OP_RETURN(op, I, asm_op, c_op) \
46-
static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
45+
#define ATOMIC_OP_RETURN(op, I, asm_op, c_op, mb, suffix) \
46+
static inline int arch_atomic_##op##_return##suffix(int i, atomic_t *v) \
4747
{ \
4848
int result; \
4949
\
5050
__asm__ __volatile__( \
51-
"am"#asm_op"_db.w" " %1, %2, %0 \n" \
51+
"am"#asm_op#mb".w" " %1, %2, %0 \n" \
5252
: "+ZB" (v->counter), "=&r" (result) \
5353
: "r" (I) \
5454
: "memory"); \
5555
\
5656
return result c_op I; \
5757
}
5858

59-
#define ATOMIC_FETCH_OP(op, I, asm_op) \
60-
static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
59+
#define ATOMIC_FETCH_OP(op, I, asm_op, mb, suffix) \
60+
static inline int arch_atomic_fetch_##op##suffix(int i, atomic_t *v) \
6161
{ \
6262
int result; \
6363
\
6464
__asm__ __volatile__( \
65-
"am"#asm_op"_db.w" " %1, %2, %0 \n" \
65+
"am"#asm_op#mb".w" " %1, %2, %0 \n" \
6666
: "+ZB" (v->counter), "=&r" (result) \
6767
: "r" (I) \
6868
: "memory"); \
@@ -72,29 +72,53 @@ static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
7272

7373
#define ATOMIC_OPS(op, I, asm_op, c_op) \
7474
ATOMIC_OP(op, I, asm_op) \
75-
ATOMIC_OP_RETURN(op, I, asm_op, c_op) \
76-
ATOMIC_FETCH_OP(op, I, asm_op)
75+
ATOMIC_OP_RETURN(op, I, asm_op, c_op, _db, ) \
76+
ATOMIC_OP_RETURN(op, I, asm_op, c_op, , _relaxed) \
77+
ATOMIC_FETCH_OP(op, I, asm_op, _db, ) \
78+
ATOMIC_FETCH_OP(op, I, asm_op, , _relaxed)
7779

7880
ATOMIC_OPS(add, i, add, +)
7981
ATOMIC_OPS(sub, -i, add, +)
8082

83+
#define arch_atomic_add_return arch_atomic_add_return
84+
#define arch_atomic_add_return_acquire arch_atomic_add_return
85+
#define arch_atomic_add_return_release arch_atomic_add_return
8186
#define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed
87+
#define arch_atomic_sub_return arch_atomic_sub_return
88+
#define arch_atomic_sub_return_acquire arch_atomic_sub_return
89+
#define arch_atomic_sub_return_release arch_atomic_sub_return
8290
#define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed
91+
#define arch_atomic_fetch_add arch_atomic_fetch_add
92+
#define arch_atomic_fetch_add_acquire arch_atomic_fetch_add
93+
#define arch_atomic_fetch_add_release arch_atomic_fetch_add
8394
#define arch_atomic_fetch_add_relaxed arch_atomic_fetch_add_relaxed
95+
#define arch_atomic_fetch_sub arch_atomic_fetch_sub
96+
#define arch_atomic_fetch_sub_acquire arch_atomic_fetch_sub
97+
#define arch_atomic_fetch_sub_release arch_atomic_fetch_sub
8498
#define arch_atomic_fetch_sub_relaxed arch_atomic_fetch_sub_relaxed
8599

86100
#undef ATOMIC_OPS
87101

88102
#define ATOMIC_OPS(op, I, asm_op) \
89103
ATOMIC_OP(op, I, asm_op) \
90-
ATOMIC_FETCH_OP(op, I, asm_op)
104+
ATOMIC_FETCH_OP(op, I, asm_op, _db, ) \
105+
ATOMIC_FETCH_OP(op, I, asm_op, , _relaxed)
91106

92107
ATOMIC_OPS(and, i, and)
93108
ATOMIC_OPS(or, i, or)
94109
ATOMIC_OPS(xor, i, xor)
95110

111+
#define arch_atomic_fetch_and arch_atomic_fetch_and
112+
#define arch_atomic_fetch_and_acquire arch_atomic_fetch_and
113+
#define arch_atomic_fetch_and_release arch_atomic_fetch_and
96114
#define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed
115+
#define arch_atomic_fetch_or arch_atomic_fetch_or
116+
#define arch_atomic_fetch_or_acquire arch_atomic_fetch_or
117+
#define arch_atomic_fetch_or_release arch_atomic_fetch_or
97118
#define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed
119+
#define arch_atomic_fetch_xor arch_atomic_fetch_xor
120+
#define arch_atomic_fetch_xor_acquire arch_atomic_fetch_xor
121+
#define arch_atomic_fetch_xor_release arch_atomic_fetch_xor
98122
#define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed
99123

100124
#undef ATOMIC_OPS
@@ -172,32 +196,32 @@ static inline int arch_atomic_sub_if_positive(int i, atomic_t *v)
172196
static inline void arch_atomic64_##op(long i, atomic64_t *v) \
173197
{ \
174198
__asm__ __volatile__( \
175-
"am"#asm_op"_db.d " " $zero, %1, %0 \n" \
199+
"am"#asm_op".d " " $zero, %1, %0 \n" \
176200
: "+ZB" (v->counter) \
177201
: "r" (I) \
178202
: "memory"); \
179203
}
180204

181-
#define ATOMIC64_OP_RETURN(op, I, asm_op, c_op) \
182-
static inline long arch_atomic64_##op##_return_relaxed(long i, atomic64_t *v) \
205+
#define ATOMIC64_OP_RETURN(op, I, asm_op, c_op, mb, suffix) \
206+
static inline long arch_atomic64_##op##_return##suffix(long i, atomic64_t *v) \
183207
{ \
184208
long result; \
185209
__asm__ __volatile__( \
186-
"am"#asm_op"_db.d " " %1, %2, %0 \n" \
210+
"am"#asm_op#mb".d " " %1, %2, %0 \n" \
187211
: "+ZB" (v->counter), "=&r" (result) \
188212
: "r" (I) \
189213
: "memory"); \
190214
\
191215
return result c_op I; \
192216
}
193217

194-
#define ATOMIC64_FETCH_OP(op, I, asm_op) \
195-
static inline long arch_atomic64_fetch_##op##_relaxed(long i, atomic64_t *v) \
218+
#define ATOMIC64_FETCH_OP(op, I, asm_op, mb, suffix) \
219+
static inline long arch_atomic64_fetch_##op##suffix(long i, atomic64_t *v) \
196220
{ \
197221
long result; \
198222
\
199223
__asm__ __volatile__( \
200-
"am"#asm_op"_db.d " " %1, %2, %0 \n" \
224+
"am"#asm_op#mb".d " " %1, %2, %0 \n" \
201225
: "+ZB" (v->counter), "=&r" (result) \
202226
: "r" (I) \
203227
: "memory"); \
@@ -207,29 +231,53 @@ static inline long arch_atomic64_fetch_##op##_relaxed(long i, atomic64_t *v) \
207231

208232
#define ATOMIC64_OPS(op, I, asm_op, c_op) \
209233
ATOMIC64_OP(op, I, asm_op) \
210-
ATOMIC64_OP_RETURN(op, I, asm_op, c_op) \
211-
ATOMIC64_FETCH_OP(op, I, asm_op)
234+
ATOMIC64_OP_RETURN(op, I, asm_op, c_op, _db, ) \
235+
ATOMIC64_OP_RETURN(op, I, asm_op, c_op, , _relaxed) \
236+
ATOMIC64_FETCH_OP(op, I, asm_op, _db, ) \
237+
ATOMIC64_FETCH_OP(op, I, asm_op, , _relaxed)
212238

213239
ATOMIC64_OPS(add, i, add, +)
214240
ATOMIC64_OPS(sub, -i, add, +)
215241

242+
#define arch_atomic64_add_return arch_atomic64_add_return
243+
#define arch_atomic64_add_return_acquire arch_atomic64_add_return
244+
#define arch_atomic64_add_return_release arch_atomic64_add_return
216245
#define arch_atomic64_add_return_relaxed arch_atomic64_add_return_relaxed
246+
#define arch_atomic64_sub_return arch_atomic64_sub_return
247+
#define arch_atomic64_sub_return_acquire arch_atomic64_sub_return
248+
#define arch_atomic64_sub_return_release arch_atomic64_sub_return
217249
#define arch_atomic64_sub_return_relaxed arch_atomic64_sub_return_relaxed
250+
#define arch_atomic64_fetch_add arch_atomic64_fetch_add
251+
#define arch_atomic64_fetch_add_acquire arch_atomic64_fetch_add
252+
#define arch_atomic64_fetch_add_release arch_atomic64_fetch_add
218253
#define arch_atomic64_fetch_add_relaxed arch_atomic64_fetch_add_relaxed
254+
#define arch_atomic64_fetch_sub arch_atomic64_fetch_sub
255+
#define arch_atomic64_fetch_sub_acquire arch_atomic64_fetch_sub
256+
#define arch_atomic64_fetch_sub_release arch_atomic64_fetch_sub
219257
#define arch_atomic64_fetch_sub_relaxed arch_atomic64_fetch_sub_relaxed
220258

221259
#undef ATOMIC64_OPS
222260

223261
#define ATOMIC64_OPS(op, I, asm_op) \
224262
ATOMIC64_OP(op, I, asm_op) \
225-
ATOMIC64_FETCH_OP(op, I, asm_op)
263+
ATOMIC64_FETCH_OP(op, I, asm_op, _db, ) \
264+
ATOMIC64_FETCH_OP(op, I, asm_op, , _relaxed)
226265

227266
ATOMIC64_OPS(and, i, and)
228267
ATOMIC64_OPS(or, i, or)
229268
ATOMIC64_OPS(xor, i, xor)
230269

270+
#define arch_atomic64_fetch_and arch_atomic64_fetch_and
271+
#define arch_atomic64_fetch_and_acquire arch_atomic64_fetch_and
272+
#define arch_atomic64_fetch_and_release arch_atomic64_fetch_and
231273
#define arch_atomic64_fetch_and_relaxed arch_atomic64_fetch_and_relaxed
274+
#define arch_atomic64_fetch_or arch_atomic64_fetch_or
275+
#define arch_atomic64_fetch_or_acquire arch_atomic64_fetch_or
276+
#define arch_atomic64_fetch_or_release arch_atomic64_fetch_or
232277
#define arch_atomic64_fetch_or_relaxed arch_atomic64_fetch_or_relaxed
278+
#define arch_atomic64_fetch_xor arch_atomic64_fetch_xor
279+
#define arch_atomic64_fetch_xor_acquire arch_atomic64_fetch_xor
280+
#define arch_atomic64_fetch_xor_release arch_atomic64_fetch_xor
233281
#define arch_atomic64_fetch_xor_relaxed arch_atomic64_fetch_xor_relaxed
234282

235283
#undef ATOMIC64_OPS

‎arch/loongarch/include/asm/inst.h‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -65,6 +65,8 @@ enum reg2_op {
6565
revbd_op = 0x0f,
6666
revh2w_op = 0x10,
6767
revhd_op = 0x11,
68+
extwh_op = 0x16,
69+
extwb_op = 0x17,
6870
iocsrrdb_op = 0x19200,
6971
iocsrrdh_op = 0x19201,
7072
iocsrrdw_op = 0x19202,
@@ -572,6 +574,8 @@ static inline void emit_##NAME(union loongarch_instruction *insn, \
572574
DEF_EMIT_REG2_FORMAT(revb2h, revb2h_op)
573575
DEF_EMIT_REG2_FORMAT(revb2w, revb2w_op)
574576
DEF_EMIT_REG2_FORMAT(revbd, revbd_op)
577+
DEF_EMIT_REG2_FORMAT(extwh, extwh_op)
578+
DEF_EMIT_REG2_FORMAT(extwb, extwb_op)
575579

576580
#define DEF_EMIT_REG2I5_FORMAT(NAME, OP) \
577581
static inline void emit_##NAME(union loongarch_instruction *insn, \
@@ -623,6 +627,9 @@ DEF_EMIT_REG2I12_FORMAT(lu52id, lu52id_op)
623627
DEF_EMIT_REG2I12_FORMAT(andi, andi_op)
624628
DEF_EMIT_REG2I12_FORMAT(ori, ori_op)
625629
DEF_EMIT_REG2I12_FORMAT(xori, xori_op)
630+
DEF_EMIT_REG2I12_FORMAT(ldb, ldb_op)
631+
DEF_EMIT_REG2I12_FORMAT(ldh, ldh_op)
632+
DEF_EMIT_REG2I12_FORMAT(ldw, ldw_op)
626633
DEF_EMIT_REG2I12_FORMAT(ldbu, ldbu_op)
627634
DEF_EMIT_REG2I12_FORMAT(ldhu, ldhu_op)
628635
DEF_EMIT_REG2I12_FORMAT(ldwu, ldwu_op)
@@ -701,9 +708,12 @@ static inline void emit_##NAME(union loongarch_instruction *insn, \
701708
insn->reg3_format.rk = rk; \
702709
}
703710

711+
DEF_EMIT_REG3_FORMAT(addw, addw_op)
704712
DEF_EMIT_REG3_FORMAT(addd, addd_op)
705713
DEF_EMIT_REG3_FORMAT(subd, subd_op)
706714
DEF_EMIT_REG3_FORMAT(muld, muld_op)
715+
DEF_EMIT_REG3_FORMAT(divd, divd_op)
716+
DEF_EMIT_REG3_FORMAT(modd, modd_op)
707717
DEF_EMIT_REG3_FORMAT(divdu, divdu_op)
708718
DEF_EMIT_REG3_FORMAT(moddu, moddu_op)
709719
DEF_EMIT_REG3_FORMAT(and, and_op)
@@ -715,6 +725,9 @@ DEF_EMIT_REG3_FORMAT(srlw, srlw_op)
715725
DEF_EMIT_REG3_FORMAT(srld, srld_op)
716726
DEF_EMIT_REG3_FORMAT(sraw, sraw_op)
717727
DEF_EMIT_REG3_FORMAT(srad, srad_op)
728+
DEF_EMIT_REG3_FORMAT(ldxb, ldxb_op)
729+
DEF_EMIT_REG3_FORMAT(ldxh, ldxh_op)
730+
DEF_EMIT_REG3_FORMAT(ldxw, ldxw_op)
718731
DEF_EMIT_REG3_FORMAT(ldxbu, ldxbu_op)
719732
DEF_EMIT_REG3_FORMAT(ldxhu, ldxhu_op)
720733
DEF_EMIT_REG3_FORMAT(ldxwu, ldxwu_op)

‎arch/loongarch/include/asm/percpu.h‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ static inline void set_my_cpu_offset(unsigned long off)
3232
#define __my_cpu_offset __my_cpu_offset
3333

3434
#define PERCPU_OP(op, asm_op, c_op) \
35-
static inline unsigned long __percpu_##op(void *ptr, \
35+
static __always_inline unsigned long __percpu_##op(void *ptr, \
3636
unsigned long val, int size) \
3737
{ \
3838
unsigned long ret; \
@@ -63,7 +63,7 @@ PERCPU_OP(and, and, &)
6363
PERCPU_OP(or, or, |)
6464
#undef PERCPU_OP
6565

66-
static inline unsigned long __percpu_read(void *ptr, int size)
66+
static __always_inline unsigned long __percpu_read(void *ptr, int size)
6767
{
6868
unsigned long ret;
6969

@@ -100,7 +100,7 @@ static inline unsigned long __percpu_read(void *ptr, int size)
100100
return ret;
101101
}
102102

103-
static inline void __percpu_write(void *ptr, unsigned long val, int size)
103+
static __always_inline void __percpu_write(void *ptr, unsigned long val, int size)
104104
{
105105
switch (size) {
106106
case 1:
@@ -132,8 +132,8 @@ static inline void __percpu_write(void *ptr, unsigned long val, int size)
132132
}
133133
}
134134

135-
static inline unsigned long __percpu_xchg(void *ptr, unsigned long val,
136-
int size)
135+
static __always_inline unsigned long __percpu_xchg(void *ptr, unsigned long val,
136+
int size)
137137
{
138138
switch (size) {
139139
case 1:

‎arch/loongarch/kernel/smp.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -504,8 +504,9 @@ asmlinkage void start_secondary(void)
504504
unsigned int cpu;
505505

506506
sync_counter();
507-
cpu = smp_processor_id();
507+
cpu = raw_smp_processor_id();
508508
set_my_cpu_offset(per_cpu_offset(cpu));
509+
rcutree_report_cpu_starting(cpu);
509510

510511
cpu_probe();
511512
constant_clockevent_init();

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