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lines changed Original file line number Diff line number Diff line change @@ -38,6 +38,15 @@ config CLK_SOPHGO_SG2042_RPGATE
3838 clock from Clock Generator IP as input.
3939 This driver provides Gate function for RP.
4040
41+ config CLK_SOPHGO_SG2044
42+ tristate "Sophgo SG2044 clock controller support"
43+ depends on ARCH_SOPHGO || COMPILE_TEST
44+ help
45+ This driver supports the clock controller on the Sophgo SG2044
46+ SoC. This controller requires mulitple PLL clock as input.
47+ This clock control provides PLL clocks and common clock function
48+ for various IPs on the SoC.
49+
4150config CLK_SOPHGO_SG2044_PLL
4251 tristate "Sophgo SG2044 PLL clock controller support"
4352 depends on ARCH_SOPHGO || COMPILE_TEST
Original file line number Diff line number Diff line change @@ -9,4 +9,5 @@ clk-sophgo-cv1800-y += clk-cv18xx-pll.o
99obj-$(CONFIG_CLK_SOPHGO_SG2042_CLKGEN) += clk-sg2042-clkgen.o
1010obj-$(CONFIG_CLK_SOPHGO_SG2042_PLL) += clk-sg2042-pll.o
1111obj-$(CONFIG_CLK_SOPHGO_SG2042_RPGATE) += clk-sg2042-rpgate.o
12+ obj-$(CONFIG_CLK_SOPHGO_SG2044) += clk-sg2044.o
1213obj-$(CONFIG_CLK_SOPHGO_SG2044_PLL) += clk-sg2044-pll.o
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