44
55#include <linux/interrupt.h>
66#include <linux/clockchips.h>
7+ #include <linux/slab.h>
78
89#include "timer-of.h"
910
2021
2122#define SYS_CTR_CLK_DIV 0x3
2223
23- static void __iomem * sys_ctr_base __ro_after_init ;
24- static u32 cmpcr __ro_after_init ;
24+ struct sysctr_private {
25+ u32 cmpcr ;
26+ };
2527
26- static void sysctr_timer_enable (bool enable )
28+ static void sysctr_timer_enable (struct clock_event_device * evt , bool enable )
2729{
28- writel (enable ? cmpcr | SYS_CTR_EN : cmpcr , sys_ctr_base + CMPCR );
30+ struct timer_of * to = to_timer_of (evt );
31+ struct sysctr_private * priv = to -> private_data ;
32+ void __iomem * base = timer_of_base (to );
33+
34+ writel (enable ? priv -> cmpcr | SYS_CTR_EN : priv -> cmpcr , base + CMPCR );
2935}
3036
31- static void sysctr_irq_acknowledge (void )
37+ static void sysctr_irq_acknowledge (struct clock_event_device * evt )
3238{
3339 /*
3440 * clear the enable bit(EN =0) will clear
3541 * the status bit(ISTAT = 0), then the interrupt
3642 * signal will be negated(acknowledged).
3743 */
38- sysctr_timer_enable (false);
44+ sysctr_timer_enable (evt , false);
3945}
4046
41- static inline u64 sysctr_read_counter (void )
47+ static inline u64 sysctr_read_counter (struct clock_event_device * evt )
4248{
49+ struct timer_of * to = to_timer_of (evt );
50+ void __iomem * base = timer_of_base (to );
4351 u32 cnt_hi , tmp_hi , cnt_lo ;
4452
4553 do {
46- cnt_hi = readl_relaxed (sys_ctr_base + CNTCV_HI );
47- cnt_lo = readl_relaxed (sys_ctr_base + CNTCV_LO );
48- tmp_hi = readl_relaxed (sys_ctr_base + CNTCV_HI );
54+ cnt_hi = readl_relaxed (base + CNTCV_HI );
55+ cnt_lo = readl_relaxed (base + CNTCV_LO );
56+ tmp_hi = readl_relaxed (base + CNTCV_HI );
4957 } while (tmp_hi != cnt_hi );
5058
5159 return ((u64 ) cnt_hi << 32 ) | cnt_lo ;
@@ -54,22 +62,24 @@ static inline u64 sysctr_read_counter(void)
5462static int sysctr_set_next_event (unsigned long delta ,
5563 struct clock_event_device * evt )
5664{
65+ struct timer_of * to = to_timer_of (evt );
66+ void __iomem * base = timer_of_base (to );
5767 u32 cmp_hi , cmp_lo ;
5868 u64 next ;
5969
60- sysctr_timer_enable (false);
70+ sysctr_timer_enable (evt , false);
6171
62- next = sysctr_read_counter ();
72+ next = sysctr_read_counter (evt );
6373
6474 next += delta ;
6575
6676 cmp_hi = (next >> 32 ) & 0x00fffff ;
6777 cmp_lo = next & 0xffffffff ;
6878
69- writel_relaxed (cmp_hi , sys_ctr_base + CMPCV_HI );
70- writel_relaxed (cmp_lo , sys_ctr_base + CMPCV_LO );
79+ writel_relaxed (cmp_hi , base + CMPCV_HI );
80+ writel_relaxed (cmp_lo , base + CMPCV_LO );
7181
72- sysctr_timer_enable (true);
82+ sysctr_timer_enable (evt , true);
7383
7484 return 0 ;
7585}
@@ -81,7 +91,7 @@ static int sysctr_set_state_oneshot(struct clock_event_device *evt)
8191
8292static int sysctr_set_state_shutdown (struct clock_event_device * evt )
8393{
84- sysctr_timer_enable (false);
94+ sysctr_timer_enable (evt , false);
8595
8696 return 0 ;
8797}
@@ -90,7 +100,7 @@ static irqreturn_t sysctr_timer_interrupt(int irq, void *dev_id)
90100{
91101 struct clock_event_device * evt = dev_id ;
92102
93- sysctr_irq_acknowledge ();
103+ sysctr_irq_acknowledge (evt );
94104
95105 evt -> event_handler (evt );
96106
@@ -117,34 +127,36 @@ static struct timer_of to_sysctr = {
117127 },
118128};
119129
120- static void __init sysctr_clockevent_init (void )
121- {
122- to_sysctr .clkevt .cpumask = cpu_possible_mask ;
123-
124- clockevents_config_and_register (& to_sysctr .clkevt ,
125- timer_of_rate (& to_sysctr ),
126- 0xff , 0x7fffffff );
127- }
128-
129130static int __init sysctr_timer_init (struct device_node * np )
130131{
131- int ret = 0 ;
132+ struct sysctr_private * priv ;
133+ void __iomem * base ;
134+ int ret ;
135+
136+ priv = kzalloc (sizeof (struct sysctr_private ), GFP_KERNEL );
137+ if (!priv )
138+ return - ENOMEM ;
132139
133140 ret = timer_of_init (np , & to_sysctr );
134- if (ret )
141+ if (ret ) {
142+ kfree (priv );
135143 return ret ;
144+ }
136145
137146 if (!of_property_read_bool (np , "nxp,no-divider" )) {
138147 /* system counter clock is divided by 3 internally */
139148 to_sysctr .of_clk .rate /= SYS_CTR_CLK_DIV ;
140149 }
141150
142- sys_ctr_base = timer_of_base (& to_sysctr );
143- cmpcr = readl (sys_ctr_base + CMPCR );
144- cmpcr &= ~SYS_CTR_EN ;
151+ to_sysctr .clkevt .cpumask = cpu_possible_mask ;
152+ to_sysctr .private_data = priv ;
145153
146- sysctr_clockevent_init ();
154+ base = timer_of_base (& to_sysctr );
155+ priv -> cmpcr = readl (base + CMPCR ) & ~SYS_CTR_EN ;
147156
157+ clockevents_config_and_register (& to_sysctr .clkevt ,
158+ timer_of_rate (& to_sysctr ),
159+ 0xff , 0x7fffffff );
148160 return 0 ;
149161}
150162TIMER_OF_DECLARE (sysctr_timer , "nxp,sysctr-timer" , sysctr_timer_init );
0 commit comments