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Merge tag 'samsung-clk-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung SoC clock driver updates from Krzysztof Kozlowski: - Add Samsung ExynosAutov920 CPU cluster CL0, CL1 and CL2 clock controllers - Fix Samsung ExynosAutov920 HSI1 USBDRD clock parents - Minor cleanup for Samsung Exynos4 clk drivers * tag 'samsung-clk-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: correct clock summary for hsi1 block clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition clk: samsung: exynosautov920: add cpucl1/2 clock support dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions clk: samsung: exynosautov920: add cpucl0 clock support dt-bindings: clock: exynosautov920: add cpucl0 clock definitions clk: samsung: Use samsung CCF common function
2 parents 0af2f6b + 8121418 commit 3a4c538

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lines changed

‎Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml‎

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ title: Samsung ExynosAuto v920 SoC clock controller
88

99
maintainers:
1010
- Sunyeal Hong <sunyeal.hong@samsung.com>
11+
- Shin Son <shin.son@samsung.com>
1112
- Chanwoo Choi <cw00.choi@samsung.com>
1213
- Krzysztof Kozlowski <krzk@kernel.org>
1314
- Sylwester Nawrocki <s.nawrocki@samsung.com>
@@ -32,6 +33,9 @@ properties:
3233
compatible:
3334
enum:
3435
- samsung,exynosautov920-cmu-top
36+
- samsung,exynosautov920-cmu-cpucl0
37+
- samsung,exynosautov920-cmu-cpucl1
38+
- samsung,exynosautov920-cmu-cpucl2
3539
- samsung,exynosautov920-cmu-peric0
3640
- samsung,exynosautov920-cmu-peric1
3741
- samsung,exynosautov920-cmu-misc
@@ -69,6 +73,71 @@ allOf:
6973
items:
7074
- const: oscclk
7175

76+
- if:
77+
properties:
78+
compatible:
79+
contains:
80+
enum:
81+
- samsung,exynosautov920-cmu-cpucl0
82+
83+
then:
84+
properties:
85+
clocks:
86+
items:
87+
- description: External reference clock (38.4 MHz)
88+
- description: CMU_CPUCL0 SWITCH clock (from CMU_TOP)
89+
- description: CMU_CPUCL0 CLUSTER clock (from CMU_TOP)
90+
- description: CMU_CPUCL0 DBG clock (from CMU_TOP)
91+
92+
clock-names:
93+
items:
94+
- const: oscclk
95+
- const: switch
96+
- const: cluster
97+
- const: dbg
98+
99+
- if:
100+
properties:
101+
compatible:
102+
contains:
103+
enum:
104+
- samsung,exynosautov920-cmu-cpucl1
105+
106+
then:
107+
properties:
108+
clocks:
109+
items:
110+
- description: External reference clock (38.4 MHz)
111+
- description: CMU_CPUCL1 SWITCH clock (from CMU_TOP)
112+
- description: CMU_CPUCL1 CLUSTER clock (from CMU_TOP)
113+
114+
clock-names:
115+
items:
116+
- const: oscclk
117+
- const: switch
118+
- const: cluster
119+
120+
- if:
121+
properties:
122+
compatible:
123+
contains:
124+
enum:
125+
- samsung,exynosautov920-cmu-cpucl2
126+
127+
then:
128+
properties:
129+
clocks:
130+
items:
131+
- description: External reference clock (38.4 MHz)
132+
- description: CMU_CPUCL2 SWITCH clock (from CMU_TOP)
133+
- description: CMU_CPUCL2 CLUSTER clock (from CMU_TOP)
134+
135+
clock-names:
136+
items:
137+
- const: oscclk
138+
- const: switch
139+
- const: cluster
140+
72141
- if:
73142
properties:
74143
compatible:

‎drivers/clk/samsung/clk-exynos4.c‎

Lines changed: 42 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -1269,6 +1269,45 @@ static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = {
12691269
CPUCLK_LAYOUT_E4210, e4412_armclk_d),
12701270
};
12711271

1272+
static const struct samsung_cmu_info cmu_info_exynos4 __initconst = {
1273+
.mux_clks = exynos4_mux_clks,
1274+
.nr_mux_clks = ARRAY_SIZE(exynos4_mux_clks),
1275+
.div_clks = exynos4_div_clks,
1276+
.nr_div_clks = ARRAY_SIZE(exynos4_div_clks),
1277+
.gate_clks = exynos4_gate_clks,
1278+
.nr_gate_clks = ARRAY_SIZE(exynos4_gate_clks),
1279+
.fixed_factor_clks = exynos4_fixed_factor_clks,
1280+
.nr_fixed_factor_clks = ARRAY_SIZE(exynos4_fixed_factor_clks),
1281+
.fixed_clks = exynos4_fixed_rate_clks,
1282+
.nr_fixed_clks = ARRAY_SIZE(exynos4_fixed_rate_clks),
1283+
};
1284+
1285+
static const struct samsung_cmu_info cmu_info_exynos4210 __initconst = {
1286+
.mux_clks = exynos4210_mux_clks,
1287+
.nr_mux_clks = ARRAY_SIZE(exynos4210_mux_clks),
1288+
.div_clks = exynos4210_div_clks,
1289+
.nr_div_clks = ARRAY_SIZE(exynos4210_div_clks),
1290+
.gate_clks = exynos4210_gate_clks,
1291+
.nr_gate_clks = ARRAY_SIZE(exynos4210_gate_clks),
1292+
.fixed_factor_clks = exynos4210_fixed_factor_clks,
1293+
.nr_fixed_factor_clks = ARRAY_SIZE(exynos4210_fixed_factor_clks),
1294+
.fixed_clks = exynos4210_fixed_rate_clks,
1295+
.nr_fixed_clks = ARRAY_SIZE(exynos4210_fixed_rate_clks),
1296+
.cpu_clks = exynos4210_cpu_clks,
1297+
.nr_cpu_clks = ARRAY_SIZE(exynos4210_cpu_clks),
1298+
};
1299+
1300+
static const struct samsung_cmu_info cmu_info_exynos4x12 __initconst = {
1301+
.mux_clks = exynos4x12_mux_clks,
1302+
.nr_mux_clks = ARRAY_SIZE(exynos4x12_mux_clks),
1303+
.div_clks = exynos4x12_div_clks,
1304+
.nr_div_clks = ARRAY_SIZE(exynos4x12_div_clks),
1305+
.gate_clks = exynos4x12_gate_clks,
1306+
.nr_gate_clks = ARRAY_SIZE(exynos4x12_gate_clks),
1307+
.fixed_factor_clks = exynos4x12_fixed_factor_clks,
1308+
.nr_fixed_factor_clks = ARRAY_SIZE(exynos4x12_fixed_factor_clks),
1309+
};
1310+
12721311
/* register exynos4 clocks */
12731312
static void __init exynos4_clk_init(struct device_node *np,
12741313
enum exynos4_soc soc)
@@ -1322,41 +1361,12 @@ static void __init exynos4_clk_init(struct device_node *np,
13221361
ARRAY_SIZE(exynos4x12_plls));
13231362
}
13241363

1325-
samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
1326-
ARRAY_SIZE(exynos4_fixed_rate_clks));
1327-
samsung_clk_register_mux(ctx, exynos4_mux_clks,
1328-
ARRAY_SIZE(exynos4_mux_clks));
1329-
samsung_clk_register_div(ctx, exynos4_div_clks,
1330-
ARRAY_SIZE(exynos4_div_clks));
1331-
samsung_clk_register_gate(ctx, exynos4_gate_clks,
1332-
ARRAY_SIZE(exynos4_gate_clks));
1333-
samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
1334-
ARRAY_SIZE(exynos4_fixed_factor_clks));
1364+
samsung_cmu_register_clocks(ctx, &cmu_info_exynos4);
13351365

13361366
if (exynos4_soc == EXYNOS4210) {
1337-
samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
1338-
ARRAY_SIZE(exynos4210_fixed_rate_clks));
1339-
samsung_clk_register_mux(ctx, exynos4210_mux_clks,
1340-
ARRAY_SIZE(exynos4210_mux_clks));
1341-
samsung_clk_register_div(ctx, exynos4210_div_clks,
1342-
ARRAY_SIZE(exynos4210_div_clks));
1343-
samsung_clk_register_gate(ctx, exynos4210_gate_clks,
1344-
ARRAY_SIZE(exynos4210_gate_clks));
1345-
samsung_clk_register_fixed_factor(ctx,
1346-
exynos4210_fixed_factor_clks,
1347-
ARRAY_SIZE(exynos4210_fixed_factor_clks));
1348-
samsung_clk_register_cpu(ctx, exynos4210_cpu_clks,
1349-
ARRAY_SIZE(exynos4210_cpu_clks));
1367+
samsung_cmu_register_clocks(ctx, &cmu_info_exynos4210);
13501368
} else {
1351-
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
1352-
ARRAY_SIZE(exynos4x12_mux_clks));
1353-
samsung_clk_register_div(ctx, exynos4x12_div_clks,
1354-
ARRAY_SIZE(exynos4x12_div_clks));
1355-
samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
1356-
ARRAY_SIZE(exynos4x12_gate_clks));
1357-
samsung_clk_register_fixed_factor(ctx,
1358-
exynos4x12_fixed_factor_clks,
1359-
ARRAY_SIZE(exynos4x12_fixed_factor_clks));
1369+
samsung_cmu_register_clocks(ctx, &cmu_info_exynos4x12);
13601370
if (soc == EXYNOS4412)
13611371
samsung_clk_register_cpu(ctx, exynos4412_cpu_clks,
13621372
ARRAY_SIZE(exynos4412_cpu_clks));

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