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Merge branch 'pci/controller/stm32'
- Update pinctrl documentation of initial states and use in runtime suspend/resume (Christian Bruel) - Add pinctrl_pm_select_init_state() for use by stm32 driver, which needs it during resume (Christian Bruel) - Add devicetree bindings and drivers for the STMicroelectronics STM32MP25 in host and endpoint modes (Christian Bruel) * pci/controller/stm32: MAINTAINERS: Add entry for ST STM32MP25 PCIe drivers PCI: stm32-ep: Add PCIe Endpoint support for STM32MP25 dt-bindings: PCI: Add STM32MP25 PCIe Endpoint bindings PCI: stm32: Add PCIe host support for STM32MP25 dt-bindings: PCI: Add STM32MP25 PCIe Root Complex bindings pinctrl: Add pinctrl_pm_select_init_state helper function Documentation: pinctrl: Describe PM helper functions for standard states.
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‎Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml‎

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/st,stm32-pcie-common.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STM32MP25 PCIe RC/EP controller
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maintainers:
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- Christian Bruel <christian.bruel@foss.st.com>
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description:
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STM32MP25 PCIe RC/EP common properties
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properties:
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clocks:
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maxItems: 1
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description: PCIe system clock
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resets:
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maxItems: 1
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power-domains:
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maxItems: 1
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access-controllers:
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maxItems: 1
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required:
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- clocks
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- resets
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additionalProperties: true

‎Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml‎

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/st,stm32-pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics STM32MP25 PCIe Endpoint
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maintainers:
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- Christian Bruel <christian.bruel@foss.st.com>
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description:
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PCIe endpoint controller based on the Synopsys DesignWare PCIe core.
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
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- $ref: /schemas/pci/st,stm32-pcie-common.yaml#
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properties:
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compatible:
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const: st,stm32mp25-pcie-ep
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reg:
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items:
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- description: Data Bus Interface (DBI) registers.
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- description: Data Bus Interface (DBI) shadow registers.
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- description: Internal Address Translation Unit (iATU) registers.
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- description: PCIe configuration registers.
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reg-names:
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items:
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- const: dbi
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- const: dbi2
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- const: atu
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- const: addr_space
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reset-gpios:
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description: GPIO controlled connection to PERST# signal
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maxItems: 1
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phys:
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maxItems: 1
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required:
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- phys
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- reset-gpios
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/st,stm32mp25-rcc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/st,stm32mp25-rcc.h>
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pcie-ep@48400000 {
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compatible = "st,stm32mp25-pcie-ep";
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reg = <0x48400000 0x400000>,
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<0x48500000 0x100000>,
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<0x48700000 0x80000>,
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<0x10000000 0x10000000>;
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reg-names = "dbi", "dbi2", "atu", "addr_space";
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clocks = <&rcc CK_BUS_PCIE>;
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phys = <&combophy PHY_TYPE_PCIE>;
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resets = <&rcc PCIE_R>;
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pinctrl-names = "default", "init";
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pinctrl-0 = <&pcie_pins_a>;
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pinctrl-1 = <&pcie_init_pins_a>;
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reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>;
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access-controllers = <&rifsc 68>;
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power-domains = <&CLUSTER_PD>;
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};

‎Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml‎

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/st,stm32-pcie-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics STM32MP25 PCIe Root Complex
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maintainers:
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- Christian Bruel <christian.bruel@foss.st.com>
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description:
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PCIe root complex controller based on the Synopsys DesignWare PCIe core.
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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- $ref: /schemas/pci/st,stm32-pcie-common.yaml#
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properties:
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compatible:
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const: st,stm32mp25-pcie-rc
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reg:
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items:
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- description: Data Bus Interface (DBI) registers.
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- description: PCIe configuration registers.
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reg-names:
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items:
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- const: dbi
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- const: config
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msi-parent:
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maxItems: 1
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patternProperties:
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'^pcie@[0-2],0$':
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type: object
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$ref: /schemas/pci/pci-pci-bridge.yaml#
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properties:
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reg:
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maxItems: 1
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phys:
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maxItems: 1
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reset-gpios:
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description: GPIO controlled connection to PERST# signal
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maxItems: 1
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wake-gpios:
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description: GPIO used as WAKE# input signal
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maxItems: 1
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required:
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- phys
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- ranges
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unevaluatedProperties: false
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required:
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- interrupt-map
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- interrupt-map-mask
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- ranges
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- dma-ranges
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/st,stm32mp25-rcc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/st,stm32mp25-rcc.h>
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pcie@48400000 {
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compatible = "st,stm32mp25-pcie-rc";
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device_type = "pci";
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reg = <0x48400000 0x400000>,
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<0x10000000 0x10000>;
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reg-names = "dbi", "config";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>,
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<0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>,
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<0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>;
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dma-ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>;
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clocks = <&rcc CK_BUS_PCIE>;
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resets = <&rcc PCIE_R>;
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msi-parent = <&v2m0>;
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access-controllers = <&rifsc 68>;
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power-domains = <&CLUSTER_PD>;
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pcie@0,0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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phys = <&combophy PHY_TYPE_PCIE>;
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wake-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};

‎Documentation/driver-api/pin-control.rst‎

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Pin control requests from drivers
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=================================
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When a device driver is about to probe the device core will automatically
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attempt to issue ``pinctrl_get_select_default()`` on these devices.
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When a device driver is about to probe, the device core attaches the
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standard states if they are defined in the device tree by calling
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``pinctrl_bind_pins()`` on these devices.
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Possible standard state names are: "default", "init", "sleep" and "idle".
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- if ``default`` is defined in the device tree, it is selected before
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device probe.
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- if ``init`` and ``default`` are defined in the device tree, the "init"
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state is selected before the driver probe and the "default" state is
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selected after the driver probe.
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- the ``sleep`` and ``idle`` states are for power management and can only
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be selected with the PM API bellow.
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PM interfaces
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=================
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PM runtime suspend/resume might need to execute the same init sequence as
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during probe. Since the predefined states are already attached to the
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device, the driver can activate these states explicitly with the
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following helper functions:
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- ``pinctrl_pm_select_default_state()``
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- ``pinctrl_pm_select_init_state()``
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- ``pinctrl_pm_select_sleep_state()``
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- ``pinctrl_pm_select_idle_state()``
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For example, if resuming the device depend on certain pinmux states
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.. code-block:: c
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foo_suspend()
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{
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/* suspend device */
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...
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pinctrl_pm_select_sleep_state(dev);
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}
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foo_resume()
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{
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pinctrl_pm_select_init_state(dev);
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/* resuming device */
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...
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pinctrl_pm_select_default_state(dev);
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}
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This way driver writers do not need to add any of the boilerplate code
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of the type found below. However when doing fine-grained state selection
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and not using the "default" state, you may have to do some device driver
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``PINCTRL_STATE_SLEEP`` at runtime, re-biasing or even re-muxing pins to save
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current in sleep mode.
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Another case is when the pinctrl needs to switch to a certain mode during
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probe and then revert to the default state at the end of probe. For example
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a PINMUX may need to be configured as a GPIO during probe. In this case, use
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``PINCTRL_STATE_INIT`` to switch state before probe, then move to
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``PINCTRL_STATE_DEFAULT`` at the end of probe for normal operation.
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A driver may request a certain control state to be activated, usually just the
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default state like this:
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‎MAINTAINERS‎

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S: Maintained
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F: drivers/pci/controller/dwc/pci-exynos.c
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PCI DRIVER FOR STM32MP25
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M: Christian Bruel <christian.bruel@foss.st.com>
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/st,stm32-pcie-*.yaml
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F: drivers/pci/controller/dwc/*stm32*
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1938019387
PCI DRIVER FOR SYNOPSYS DESIGNWARE
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M: Jingoo Han <jingoohan1@gmail.com>
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M: Manivannan Sadhasivam <mani@kernel.org>

‎drivers/pci/controller/dwc/Kconfig‎

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help
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Say Y here if you want PCIe support on SPEAr13XX SoCs.
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config PCIE_STM32_HOST
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tristate "STMicroelectronics STM32MP25 PCIe Controller (host mode)"
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depends on ARCH_STM32 || COMPILE_TEST
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depends on PCI_MSI
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select PCIE_DW_HOST
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help
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Enables Root Complex (RC) support for the DesignWare core based PCIe
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controller found in STM32MP25 SoC.
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This driver can also be built as a module. If so, the module
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will be called pcie-stm32.
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config PCIE_STM32_EP
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tristate "STMicroelectronics STM32MP25 PCIe Controller (endpoint mode)"
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depends on ARCH_STM32 || COMPILE_TEST
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depends on PCI_ENDPOINT
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select PCIE_DW_EP
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help
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Enables Endpoint (EP) support for the DesignWare core based PCIe
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controller found in STM32MP25 SoC.
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This driver can also be built as a module. If so, the module
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will be called pcie-stm32-ep.
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config PCI_DRA7XX
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tristate
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‎drivers/pci/controller/dwc/Makefile‎

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obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
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obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
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obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
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obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o
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obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o
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# The following drivers are for devices that use the generic ACPI
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# pci_root.c driver but don't support standard ECAM config access.

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