@@ -85,6 +85,70 @@ to CPUINTC directly::
8585 | Devices |
8686 +---------+
8787
88+ Virtual Extended IRQ model
89+ ==========================
90+
91+ In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt
92+ go to CPUINTC directly, CPU UARTS interrupts go to PCH-PIC, while all other
93+ devices interrupts go to PCH-PIC/PCH-MSI and gathered by V-EIOINTC (Virtual
94+ Extended I/O Interrupt Controller), and then go to CPUINTC directly::
95+
96+ +-----+ +-------------------+ +-------+
97+ | IPI |--> | CPUINTC(0-255vcpu)| <-- | Timer |
98+ +-----+ +-------------------+ +-------+
99+ ^
100+ |
101+ +-----------+
102+ | V-EIOINTC |
103+ +-----------+
104+ ^ ^
105+ | |
106+ +---------+ +---------+
107+ | PCH-PIC | | PCH-MSI |
108+ +---------+ +---------+
109+ ^ ^ ^
110+ | | |
111+ +--------+ +---------+ +---------+
112+ | UARTs | | Devices | | Devices |
113+ +--------+ +---------+ +---------+
114+
115+
116+ Description
117+ -----------
118+ V-EIOINTC (Virtual Extended I/O Interrupt Controller) is an extension of
119+ EIOINTC, it only works in VM mode which runs in KVM hypervisor. Interrupts can
120+ be routed to up to four vCPUs via standard EIOINTC, however with V-EIOINTC
121+ interrupts can be routed to up to 256 virtual cpus.
122+
123+ With standard EIOINTC, interrupt routing setting includes two parts: eight
124+ bits for CPU selection and four bits for CPU IP (Interrupt Pin) selection.
125+ For CPU selection there is four bits for EIOINTC node selection, four bits
126+ for EIOINTC CPU selection. Bitmap method is used for CPU selection and
127+ CPU IP selection, so interrupt can only route to CPU0 - CPU3 and IP0-IP3 in
128+ one EIOINTC node.
129+
130+ With V-EIOINTC it supports to route more CPUs and CPU IP (Interrupt Pin),
131+ there are two newly added registers with V-EIOINTC.
132+
133+ EXTIOI_VIRT_FEATURES
134+ --------------------
135+ This register is read-only register, which indicates supported features with
136+ V-EIOINTC. Feature EXTIOI_HAS_INT_ENCODE and EXTIOI_HAS_CPU_ENCODE is added.
137+
138+ Feature EXTIOI_HAS_INT_ENCODE is part of standard EIOINTC. If it is 1, it
139+ indicates that CPU Interrupt Pin selection can be normal method rather than
140+ bitmap method, so interrupt can be routed to IP0 - IP15.
141+
142+ Feature EXTIOI_HAS_CPU_ENCODE is entension of V-EIOINTC. If it is 1, it
143+ indicates that CPU selection can be normal method rather than bitmap method,
144+ so interrupt can be routed to CPU0 - CPU255.
145+
146+ EXTIOI_VIRT_CONFIG
147+ ------------------
148+ This register is read-write register, for compatibility intterupt routed uses
149+ the default method which is the same with standard EIOINTC. If the bit is set
150+ with 1, it indicated HW to use normal method rather than bitmap method.
151+
88152Advanced Extended IRQ model
89153===========================
90154
0 commit comments