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airliedairlied
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Merge tag 'drm-msm-fixes-2025-04-18' of https://gitlab.freedesktop.org/drm/msm into drm-fixes
Fixes for v6.15-rc3 Display: - Fix to call dpu_plane_atomic_check_pipe() for both SSPPs in case of multi-rect - Fix to validate plane_state pointer before using it in dpu_plane_virtual_atomic_check() - Fix to make sure dereferencing dpu_encoder_phys happens after making sure it is valid in _dpu_encoder_trigger_start() - Remove the remaining intr_tear_rd_ptr which we initialized to -1 because NO_IRQ indices start from 0 now GPU: - Fix IB_SIZE overflow Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://lore.kernel.org/r/CAF6AEGtVKXEVdzUzFWmQE8JmK3nx_hp+ynOd-5j3vnfcU-sgOA@mail.gmail.com
2 parents 3748bef + 9d78f02 commit 0467145

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10 files changed

+53
-55
lines changed

10 files changed

+53
-55
lines changed

‎drivers/gpu/drm/msm/adreno/a6xx_gpu.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -242,10 +242,10 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
242242
break;
243243
fallthrough;
244244
case MSM_SUBMIT_CMD_BUF:
245-
OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3);
245+
OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
246246
OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
247247
OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));
248-
OUT_RING(ring, submit->cmd[i].size);
248+
OUT_RING(ring, A5XX_CP_INDIRECT_BUFFER_2_IB_SIZE(submit->cmd[i].size));
249249
ibs++;
250250
break;
251251
}
@@ -377,10 +377,10 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
377377
break;
378378
fallthrough;
379379
case MSM_SUBMIT_CMD_BUF:
380-
OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3);
380+
OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
381381
OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
382382
OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));
383-
OUT_RING(ring, submit->cmd[i].size);
383+
OUT_RING(ring, A5XX_CP_INDIRECT_BUFFER_2_IB_SIZE(submit->cmd[i].size));
384384
ibs++;
385385
break;
386386
}

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,6 @@ static const struct dpu_intf_cfg msm8937_intf[] = {
132132
.prog_fetch_lines_worst_case = 14,
133133
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
134134
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
135-
.intr_tear_rd_ptr = -1,
136135
}, {
137136
.name = "intf_2", .id = INTF_2,
138137
.base = 0x6b000, .len = 0x268,
@@ -141,7 +140,6 @@ static const struct dpu_intf_cfg msm8937_intf[] = {
141140
.prog_fetch_lines_worst_case = 14,
142141
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
143142
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
144-
.intr_tear_rd_ptr = -1,
145143
},
146144
};
147145

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,6 @@ static const struct dpu_intf_cfg msm8917_intf[] = {
118118
.prog_fetch_lines_worst_case = 14,
119119
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
120120
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
121-
.intr_tear_rd_ptr = -1,
122121
},
123122
};
124123

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -131,7 +131,6 @@ static const struct dpu_intf_cfg msm8953_intf[] = {
131131
.prog_fetch_lines_worst_case = 14,
132132
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
133133
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
134-
.intr_tear_rd_ptr = -1,
135134
}, {
136135
.name = "intf_1", .id = INTF_1,
137136
.base = 0x6a800, .len = 0x268,
@@ -140,7 +139,6 @@ static const struct dpu_intf_cfg msm8953_intf[] = {
140139
.prog_fetch_lines_worst_case = 14,
141140
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
142141
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
143-
.intr_tear_rd_ptr = -1,
144142
}, {
145143
.name = "intf_2", .id = INTF_2,
146144
.base = 0x6b000, .len = 0x268,
@@ -149,7 +147,6 @@ static const struct dpu_intf_cfg msm8953_intf[] = {
149147
.prog_fetch_lines_worst_case = 14,
150148
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
151149
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
152-
.intr_tear_rd_ptr = -1,
153150
},
154151
};
155152

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -241,7 +241,6 @@ static const struct dpu_intf_cfg msm8996_intf[] = {
241241
.prog_fetch_lines_worst_case = 25,
242242
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
243243
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
244-
.intr_tear_rd_ptr = -1,
245244
}, {
246245
.name = "intf_1", .id = INTF_1,
247246
.base = 0x6a800, .len = 0x268,
@@ -250,7 +249,6 @@ static const struct dpu_intf_cfg msm8996_intf[] = {
250249
.prog_fetch_lines_worst_case = 25,
251250
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
252251
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
253-
.intr_tear_rd_ptr = -1,
254252
}, {
255253
.name = "intf_2", .id = INTF_2,
256254
.base = 0x6b000, .len = 0x268,
@@ -259,15 +257,13 @@ static const struct dpu_intf_cfg msm8996_intf[] = {
259257
.prog_fetch_lines_worst_case = 25,
260258
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
261259
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
262-
.intr_tear_rd_ptr = -1,
263260
}, {
264261
.name = "intf_3", .id = INTF_3,
265262
.base = 0x6b800, .len = 0x268,
266263
.type = INTF_HDMI,
267264
.prog_fetch_lines_worst_case = 25,
268265
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
269266
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
270-
.intr_tear_rd_ptr = -1,
271267
},
272268
};
273269

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -202,7 +202,6 @@ static const struct dpu_intf_cfg sdm660_intf[] = {
202202
.prog_fetch_lines_worst_case = 21,
203203
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
204204
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
205-
.intr_tear_rd_ptr = -1,
206205
}, {
207206
.name = "intf_1", .id = INTF_1,
208207
.base = 0x6a800, .len = 0x280,
@@ -211,7 +210,6 @@ static const struct dpu_intf_cfg sdm660_intf[] = {
211210
.prog_fetch_lines_worst_case = 21,
212211
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
213212
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
214-
.intr_tear_rd_ptr = -1,
215213
}, {
216214
.name = "intf_2", .id = INTF_2,
217215
.base = 0x6b000, .len = 0x280,
@@ -220,7 +218,6 @@ static const struct dpu_intf_cfg sdm660_intf[] = {
220218
.prog_fetch_lines_worst_case = 21,
221219
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
222220
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
223-
.intr_tear_rd_ptr = -1,
224221
},
225222
};
226223

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -147,7 +147,6 @@ static const struct dpu_intf_cfg sdm630_intf[] = {
147147
.prog_fetch_lines_worst_case = 21,
148148
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
149149
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
150-
.intr_tear_rd_ptr = -1,
151150
}, {
152151
.name = "intf_1", .id = INTF_1,
153152
.base = 0x6a800, .len = 0x280,
@@ -156,7 +155,6 @@ static const struct dpu_intf_cfg sdm630_intf[] = {
156155
.prog_fetch_lines_worst_case = 21,
157156
.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
158157
.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
159-
.intr_tear_rd_ptr = -1,
160158
},
161159
};
162160

‎drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1666,7 +1666,7 @@ static void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
16661666
*/
16671667
static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
16681668
{
1669-
struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(phys->parent);
1669+
struct dpu_encoder_virt *dpu_enc;
16701670

16711671
if (!phys) {
16721672
DPU_ERROR("invalid argument(s)\n");
@@ -1678,6 +1678,8 @@ static void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
16781678
return;
16791679
}
16801680

1681+
dpu_enc = to_dpu_encoder_virt(phys->parent);
1682+
16811683
if (phys->parent->encoder_type == DRM_MODE_ENCODER_VIRTUAL &&
16821684
dpu_enc->cwb_mask) {
16831685
DPU_DEBUG("encoder %d CWB enabled, skipping\n", DRMID(phys->parent));

‎drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c‎

Lines changed: 39 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -729,12 +729,40 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
729729
static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
730730
struct dpu_sw_pipe *pipe,
731731
struct dpu_sw_pipe_cfg *pipe_cfg,
732-
const struct msm_format *fmt,
733-
const struct drm_display_mode *mode)
732+
const struct drm_display_mode *mode,
733+
struct drm_plane_state *new_plane_state)
734734
{
735735
uint32_t min_src_size;
736736
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
737737
int ret;
738+
const struct msm_format *fmt;
739+
uint32_t supported_rotations;
740+
const struct dpu_sspp_cfg *pipe_hw_caps;
741+
const struct dpu_sspp_sub_blks *sblk;
742+
743+
pipe_hw_caps = pipe->sspp->cap;
744+
sblk = pipe->sspp->cap->sblk;
745+
746+
/*
747+
* We already have verified scaling against platform limitations.
748+
* Now check if the SSPP supports scaling at all.
749+
*/
750+
if (!sblk->scaler_blk.len &&
751+
((drm_rect_width(&new_plane_state->src) >> 16 !=
752+
drm_rect_width(&new_plane_state->dst)) ||
753+
(drm_rect_height(&new_plane_state->src) >> 16 !=
754+
drm_rect_height(&new_plane_state->dst))))
755+
return -ERANGE;
756+
757+
fmt = msm_framebuffer_format(new_plane_state->fb);
758+
759+
supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0;
760+
761+
if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION))
762+
supported_rotations |= DRM_MODE_ROTATE_90;
763+
764+
pipe_cfg->rotation = drm_rotation_simplify(new_plane_state->rotation,
765+
supported_rotations);
738766

739767
min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1;
740768

@@ -923,47 +951,20 @@ static int dpu_plane_atomic_check_sspp(struct drm_plane *plane,
923951
struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
924952
struct dpu_sw_pipe *pipe = &pstate->pipe;
925953
struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
926-
const struct msm_format *fmt;
927954
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
928955
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
929-
uint32_t supported_rotations;
930-
const struct dpu_sspp_cfg *pipe_hw_caps;
931-
const struct dpu_sspp_sub_blks *sblk;
932956
int ret = 0;
933957

934-
pipe_hw_caps = pipe->sspp->cap;
935-
sblk = pipe->sspp->cap->sblk;
936-
937-
/*
938-
* We already have verified scaling against platform limitations.
939-
* Now check if the SSPP supports scaling at all.
940-
*/
941-
if (!sblk->scaler_blk.len &&
942-
((drm_rect_width(&new_plane_state->src) >> 16 !=
943-
drm_rect_width(&new_plane_state->dst)) ||
944-
(drm_rect_height(&new_plane_state->src) >> 16 !=
945-
drm_rect_height(&new_plane_state->dst))))
946-
return -ERANGE;
947-
948-
fmt = msm_framebuffer_format(new_plane_state->fb);
949-
950-
supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0;
951-
952-
if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION))
953-
supported_rotations |= DRM_MODE_ROTATE_90;
954-
955-
pipe_cfg->rotation = drm_rotation_simplify(new_plane_state->rotation,
956-
supported_rotations);
957-
r_pipe_cfg->rotation = pipe_cfg->rotation;
958-
959-
ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt,
960-
&crtc_state->adjusted_mode);
958+
ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg,
959+
&crtc_state->adjusted_mode,
960+
new_plane_state);
961961
if (ret)
962962
return ret;
963963

964964
if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) {
965-
ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt,
966-
&crtc_state->adjusted_mode);
965+
ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg,
966+
&crtc_state->adjusted_mode,
967+
new_plane_state);
967968
if (ret)
968969
return ret;
969970
}
@@ -1059,6 +1060,9 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane,
10591060
struct drm_crtc_state *crtc_state;
10601061
int ret;
10611062

1063+
if (IS_ERR(plane_state))
1064+
return PTR_ERR(plane_state);
1065+
10621066
if (plane_state->crtc)
10631067
crtc_state = drm_atomic_get_new_crtc_state(state,
10641068
plane_state->crtc);

‎drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2259,5 +2259,12 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
22592259
</reg32>
22602260
</domain>
22612261

2262+
<domain name="CP_INDIRECT_BUFFER" width="32" varset="chip" prefix="chip" variants="A5XX-">
2263+
<reg64 offset="0" name="IB_BASE" type="address"/>
2264+
<reg32 offset="2" name="2">
2265+
<bitfield name="IB_SIZE" low="0" high="19"/>
2266+
</reg32>
2267+
</domain>
2268+
22622269
</database>
22632270

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