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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Catalin Marinas: - Expand the speculative SSBS errata workaround to more CPUs - Ensure jump label changes are visible to all CPUs with a kick_all_cpus_sync() (and also enable jump label batching as part of the fix) - The shadow call stack sanitiser is currently incompatible with Rust, make CONFIG_RUST conditional on !CONFIG_SHADOW_CALL_STACK * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: jump_label: Ensure patched jump_labels are visible to all CPUs rust: SHADOW_CALL_STACK is incompatible with Rust arm64: errata: Expand speculative SSBS workaround (again) arm64: cputype: Add Cortex-A725 definitions arm64: cputype: Add Cortex-X1C definitions
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‎Documentation/arch/arm64/silicon-errata.rst‎

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@@ -122,10 +122,18 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #1490853 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A76 | #3324349 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A77 | #1491015 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A77 | #3324348 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A78 | #3324344 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A78C | #3324346,3324347| ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |
@@ -138,8 +146,14 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A720 | #3456091 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A725 | #3456106 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X1 | #1502854 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X1C | #3324346 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 |
@@ -160,6 +174,8 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #3324349 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 |
@@ -170,6 +186,8 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V1 | #1619801 | N/A |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V1 | #3324341 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 |

‎arch/arm64/Kconfig‎

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@@ -1069,30 +1069,40 @@ config ARM64_ERRATUM_3117295
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If unsure, say Y.
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config ARM64_ERRATUM_3194386
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bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing"
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bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
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default y
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help
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This option adds the workaround for the following errata:
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* ARM Cortex-A76 erratum 3324349
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* ARM Cortex-A77 erratum 3324348
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* ARM Cortex-A78 erratum 3324344
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* ARM Cortex-A78C erratum 3324346
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* ARM Cortex-A78C erratum 3324347
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* ARM Cortex-A710 erratam 3324338
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* ARM Cortex-A720 erratum 3456091
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* ARM Cortex-A725 erratum 3456106
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* ARM Cortex-X1 erratum 3324344
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* ARM Cortex-X1C erratum 3324346
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* ARM Cortex-X2 erratum 3324338
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* ARM Cortex-X3 erratum 3324335
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* ARM Cortex-X4 erratum 3194386
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* ARM Cortex-X925 erratum 3324334
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* ARM Neoverse-N1 erratum 3324349
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* ARM Neoverse N2 erratum 3324339
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* ARM Neoverse-V1 erratum 3324341
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* ARM Neoverse V2 erratum 3324336
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* ARM Neoverse-V3 erratum 3312417
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On affected cores "MSR SSBS, #0" instructions may not affect
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subsequent speculative instructions, which may permit unexepected
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speculative store bypassing.
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Work around this problem by placing a speculation barrier after
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kernel changes to SSBS. The presence of the SSBS special-purpose
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register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such
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that userspace will use the PR_SPEC_STORE_BYPASS prctl to change
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SSBS.
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Work around this problem by placing a Speculation Barrier (SB) or
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Instruction Synchronization Barrier (ISB) after kernel changes to
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SSBS. The presence of the SSBS special-purpose register is hidden
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from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace
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will use the PR_SPEC_STORE_BYPASS prctl to change SSBS.
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If unsure, say Y.
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‎arch/arm64/include/asm/cputype.h‎

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@@ -86,12 +86,14 @@
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#define ARM_CPU_PART_CORTEX_X2 0xD48
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#define ARM_CPU_PART_NEOVERSE_N2 0xD49
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#define ARM_CPU_PART_CORTEX_A78C 0xD4B
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#define ARM_CPU_PART_CORTEX_X1C 0xD4C
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#define ARM_CPU_PART_CORTEX_X3 0xD4E
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#define ARM_CPU_PART_NEOVERSE_V2 0xD4F
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#define ARM_CPU_PART_CORTEX_A720 0xD81
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#define ARM_CPU_PART_CORTEX_X4 0xD82
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#define ARM_CPU_PART_NEOVERSE_V3 0xD84
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#define ARM_CPU_PART_CORTEX_X925 0xD85
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#define ARM_CPU_PART_CORTEX_A725 0xD87
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#define APM_CPU_PART_XGENE 0x000
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#define APM_CPU_VAR_POTENZA 0x00
@@ -165,12 +167,14 @@
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#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
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#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
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#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
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#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)
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#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3)
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#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
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#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)
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#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
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#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
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#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
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#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
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#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
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#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
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#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

‎arch/arm64/include/asm/jump_label.h‎

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#include <linux/types.h>
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#include <asm/insn.h>
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#define HAVE_JUMP_LABEL_BATCH
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#define JUMP_LABEL_NOP_SIZE AARCH64_INSN_SIZE
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#define JUMP_TABLE_ENTRY(key, label) \

‎arch/arm64/kernel/cpu_errata.c‎

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@@ -434,15 +434,24 @@ static const struct midr_range erratum_spec_unpriv_load_list[] = {
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#ifdef CONFIG_ARM64_ERRATUM_3194386
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static const struct midr_range erratum_spec_ssbs_list[] = {
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
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MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
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{}
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};
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#endif

‎arch/arm64/kernel/jump_label.c‎

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*/
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#include <linux/kernel.h>
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#include <linux/jump_label.h>
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#include <linux/smp.h>
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#include <asm/insn.h>
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#include <asm/patching.h>
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void arch_jump_label_transform(struct jump_entry *entry,
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enum jump_label_type type)
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bool arch_jump_label_transform_queue(struct jump_entry *entry,
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enum jump_label_type type)
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{
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void *addr = (void *)jump_entry_code(entry);
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u32 insn;
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}
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aarch64_insn_patch_text_nosync(addr, insn);
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return true;
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}
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void arch_jump_label_transform_apply(void)
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{
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kick_all_cpus_sync();
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}

‎init/Kconfig‎

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depends on !MODVERSIONS
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depends on !GCC_PLUGINS
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depends on !RANDSTRUCT
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depends on !SHADOW_CALL_STACK
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depends on !DEBUG_INFO_BTF || PAHOLE_HAS_LANG_EXCLUDE
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help
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Enables Rust support in the kernel.

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