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215 | 215 | #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* Disable Speculative Store Bypass. */ |
216 | 216 | #define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* AMD SSBD implementation via LS_CFG MSR */ |
217 | 217 | #define X86_FEATURE_IBRS ( 7*32+25) /* "ibrs" Indirect Branch Restricted Speculation */ |
218 | | -#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier */ |
| 218 | +#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without a guaranteed RSB flush */ |
219 | 219 | #define X86_FEATURE_STIBP ( 7*32+27) /* "stibp" Single Thread Indirect Branch Predictors */ |
220 | 220 | #define X86_FEATURE_ZEN ( 7*32+28) /* Generic flag for all Zen and newer */ |
221 | 221 | #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* L1TF workaround PTE inversion */ |
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317 | 317 | #define X86_FEATURE_ZEN1 (11*32+31) /* CPU based on Zen1 microarchitecture */ |
318 | 318 |
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319 | 319 | /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ |
| 320 | +#define X86_FEATURE_SHA512 (12*32+ 0) /* SHA512 instructions */ |
| 321 | +#define X86_FEATURE_SM3 (12*32+ 1) /* SM3 instructions */ |
| 322 | +#define X86_FEATURE_SM4 (12*32+ 2) /* SM4 instructions */ |
320 | 323 | #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* "avx_vnni" AVX VNNI instructions */ |
321 | 324 | #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* "avx512_bf16" AVX512 BFLOAT16 instructions */ |
322 | 325 | #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* CMPccXADD instructions */ |
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348 | 351 | #define X86_FEATURE_CPPC (13*32+27) /* "cppc" Collaborative Processor Performance Control */ |
349 | 352 | #define X86_FEATURE_AMD_PSFD (13*32+28) /* Predictive Store Forwarding Disable */ |
350 | 353 | #define X86_FEATURE_BTC_NO (13*32+29) /* Not vulnerable to Branch Type Confusion */ |
| 354 | +#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* IBPB clears return address predictor */ |
351 | 355 | #define X86_FEATURE_BRS (13*32+31) /* "brs" Branch Sampling available */ |
352 | 356 |
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353 | 357 | /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ |
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472 | 476 | #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* BHI_DIS_S HW control available */ |
473 | 477 | #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* BHI_DIS_S HW control enabled */ |
474 | 478 | #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */ |
475 | | -#define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* AMD Fast CPPC */ |
| 479 | +#define X86_FEATURE_AMD_FAST_CPPC (21*32 + 5) /* Fast CPPC */ |
| 480 | +#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */ |
| 481 | +#define X86_FEATURE_AMD_WORKLOAD_CLASS (21*32 + 7) /* Workload Classification */ |
476 | 482 |
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477 | 483 | /* |
478 | 484 | * BUG word(s) |
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523 | 529 | #define X86_BUG_DIV0 X86_BUG(1*32 + 1) /* "div0" AMD DIV0 speculation bug */ |
524 | 530 | #define X86_BUG_RFDS X86_BUG(1*32 + 2) /* "rfds" CPU is vulnerable to Register File Data Sampling */ |
525 | 531 | #define X86_BUG_BHI X86_BUG(1*32 + 3) /* "bhi" CPU is affected by Branch History Injection */ |
| 532 | +#define X86_BUG_IBPB_NO_RET X86_BUG(1*32 + 4) /* "ibpb_no_ret" IBPB omits return target predictions */ |
526 | 533 | #endif /* _ASM_X86_CPUFEATURES_H */ |
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