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[libcpu-riscv]: [common64 virt64]:Add the specific implementation of the spinlock.
The specific implementation of the spinlock is added in risc-v/virt64/interrupt.c. Due to the need for atomic operations, a new file atomic_riscv.c (copied from the common directory) is added under risc-v/common64. Signed-off-by: Mengchen Teng <teng_mengchen@163.com>
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‎libcpu/risc-v/common64/atomic_riscv.c‎

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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-03-14 WangShun first version
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*/
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#include <rtthread.h>
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rt_atomic_t rt_hw_atomic_exchange(volatile rt_atomic_t *ptr, rt_atomic_t val)
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{
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rt_atomic_t result = 0;
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#if __riscv_xlen == 32
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asm volatile ("amoswap.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoswap.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#endif
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return result;
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}
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rt_atomic_t rt_hw_atomic_add(volatile rt_atomic_t *ptr, rt_atomic_t val)
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{
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rt_atomic_t result = 0;
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#if __riscv_xlen == 32
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asm volatile ("amoadd.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoadd.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#endif
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return result;
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}
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rt_atomic_t rt_hw_atomic_sub(volatile rt_atomic_t *ptr, rt_atomic_t val)
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{
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rt_atomic_t result = 0;
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val = -val;
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#if __riscv_xlen == 32
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asm volatile ("amoadd.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoadd.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#endif
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return result;
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}
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rt_atomic_t rt_hw_atomic_xor(volatile rt_atomic_t *ptr, rt_atomic_t val)
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{
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rt_atomic_t result = 0;
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#if __riscv_xlen == 32
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asm volatile ("amoxor.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoxor.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#endif
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return result;
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}
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rt_atomic_t rt_hw_atomic_and(volatile rt_atomic_t *ptr, rt_atomic_t val)
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{
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rt_atomic_t result = 0;
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#if __riscv_xlen == 32
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asm volatile ("amoand.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoand.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#endif
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return result;
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}
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rt_atomic_t rt_hw_atomic_or(volatile rt_atomic_t *ptr, rt_atomic_t val)
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{
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rt_atomic_t result = 0;
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#if __riscv_xlen == 32
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asm volatile ("amoor.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoor.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#endif
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return result;
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}
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rt_atomic_t rt_hw_atomic_load(volatile rt_atomic_t *ptr)
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{
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rt_atomic_t result = 0;
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#if __riscv_xlen == 32
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asm volatile ("amoxor.w %0, x0, (%1)" : "=r"(result) : "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoxor.d %0, x0, (%1)" : "=r"(result) : "r"(ptr) : "memory");
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#endif
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return result;
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}
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void rt_hw_atomic_store(volatile rt_atomic_t *ptr, rt_atomic_t val)
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{
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rt_atomic_t result = 0;
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#if __riscv_xlen == 32
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asm volatile ("amoswap.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoswap.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory");
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#endif
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}
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rt_atomic_t rt_hw_atomic_flag_test_and_set(volatile rt_atomic_t *ptr)
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{
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rt_atomic_t result = 0;
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rt_atomic_t temp = 1;
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#if __riscv_xlen == 32
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asm volatile ("amoor.w %0, %1, (%2)" : "=r"(result) : "r"(temp), "r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoor.d %0, %1, (%2)" : "=r"(result) : "r"(temp), "r"(ptr) : "memory");
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#endif
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return result;
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}
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void rt_hw_atomic_flag_clear(volatile rt_atomic_t *ptr)
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{
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rt_atomic_t result = 0;
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#if __riscv_xlen == 32
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asm volatile ("amoand.w %0, x0, (%1)" : "=r"(result) :"r"(ptr) : "memory");
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#elif __riscv_xlen == 64
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asm volatile ("amoand.d %0, x0, (%1)" : "=r"(result) :"r"(ptr) : "memory");
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#endif
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}
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rt_atomic_t rt_hw_atomic_compare_exchange_strong(volatile rt_atomic_t *ptr, rt_atomic_t *old, rt_atomic_t desired)
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{
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rt_atomic_t tmp = *old;
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rt_atomic_t result = 0;
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#if __riscv_xlen == 32
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asm volatile(
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" fence iorw, ow\n"
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"1: lr.w.aq %[result], (%[ptr])\n"
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" bne %[result], %[tmp], 2f\n"
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" sc.w.rl %[tmp], %[desired], (%[ptr])\n"
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" bnez %[tmp], 1b\n"
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" li %[result], 1\n"
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" j 3f\n"
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" 2:sw %[result], (%[old])\n"
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" li %[result], 0\n"
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" 3:\n"
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: [result]"+r" (result), [tmp]"+r" (tmp), [ptr]"+r" (ptr)
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: [desired]"r" (desired), [old]"r"(old)
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: "memory");
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#elif __riscv_xlen == 64
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asm volatile(
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" fence iorw, ow\n"
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"1: lr.d.aq %[result], (%[ptr])\n"
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" bne %[result], %[tmp], 2f\n"
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" sc.d.rl %[tmp], %[desired], (%[ptr])\n"
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" bnez %[tmp], 1b\n"
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" li %[result], 1\n"
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" j 3f\n"
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" 2:sd %[result], (%[old])\n"
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" li %[result], 0\n"
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" 3:\n"
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: [result]"+r" (result), [tmp]"+r" (tmp), [ptr]"+r" (ptr)
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: [desired]"r" (desired), [old]"r"(old)
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: "memory");
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#endif
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return result;
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}

‎libcpu/risc-v/virt64/interrupt.c‎

Lines changed: 39 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -104,17 +104,53 @@ rt_bool_t rt_hw_interrupt_is_disabled(void)
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void rt_hw_spin_lock_init(rt_hw_spinlock_t *_lock)
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{
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// union rt_hw_spinlock_t *lock = (void *)_lock;
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// _lock->slock = 0;
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}
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void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
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{
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// /* Use ticket lock implemented on top of the 32/64-bit atomic AMO ops.
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// * The combined word layout (slock) maps two uint16_t fields:
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// * low 16 bits: owner
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// * high 16 bits: next (ticket allocator)
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// * We atomically increment the "next" field by (1 << 16) and use the
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// * returned old value to compute our ticket. Then wait until owner == ticket.
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// */
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// rt_atomic_t prev;
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// rt_atomic_t ticket;
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// rt_atomic_t owner;
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// /* Allocate a ticket by adding (1 << 16) to slock, prev holds previous value */
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// prev = rt_hw_atomic_add((volatile rt_atomic_t *)&lock->slock, (rt_atomic_t)(1UL << 16));
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// ticket = (prev >> 16) & 0xffffUL;
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// /* Wait until owner equals our ticket */
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// for (;;)
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// {
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// owner = rt_hw_atomic_load((volatile rt_atomic_t *)&lock->slock) & 0xffffUL;
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// if (owner == ticket)
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// break;
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// /* TODO: low-power wait for interrupt while spinning */
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// // __asm__ volatile("wfi" ::: "memory");
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// }
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// /* Ensure all following memory accesses are ordered after acquiring the lock */
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// __asm__ volatile("fence rw, rw" ::: "memory");
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}
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void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
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{
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// /* Ensure memory operations before unlock are visible before owner increment */
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// __asm__ volatile("fence rw, rw" ::: "memory");
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// /* Increment owner (low 16 bits) to hand over lock to next ticket */
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// rt_hw_atomic_add((volatile rt_atomic_t *)&lock->slock, (rt_atomic_t)1);
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// // TODO: IPI interrupt to wake up other harts waiting for the lock
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// /* Make the increment visible to other harts */
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// __asm__ volatile("fence rw, rw" ::: "memory");
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}
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void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)

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