[libcpu-riscv]: [surpport SMP]: Add IPI handling.

Add IPI handling logic based on the RISC-V architecture.We
handle IPI-related requests in software interrupts.
Up to this point, the RISC-V 64 architecture can support the 2-core
SMP mode and has passed the SMP Utest.

Signed-off-by: Mengchen Teng <teng_mengchen@163.com>

Author: Tm-C-mT

bsp/qemu-virt64-riscv/driver/board.c

@@ -88,6 +88,11 @@ void rt_hw_board_init(void)
 #endif /* RT_USING_CONSOLE */
 
     rt_hw_tick_init();
+    
+#ifdef RT_USING_SMP
+    /* ipi init */
+    rt_hw_ipi_init();
+#endif /* RT_USING_SMP */
 
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();

libcpu/risc-v/common64/cpuport.c

@@ -188,7 +188,12 @@ void secondary_cpu_entry(void)
     /* The PLIC peripheral interrupts are currently handled by the boot_hart. */
     /* Enable the Supervisor-Timer bit in SIE */
     rt_hw_tick_init();
-  
+    
+#ifdef RT_USING_SMP
+    /* ipi init */
+    rt_hw_ipi_init();
+#endif /* RT_USING_SMP */
+
     rt_hw_spin_lock(&_cpus_lock);
     /* invoke system scheduler start for secondary CPU */
     rt_system_scheduler_start();

libcpu/risc-v/common64/trap.c

@@ -322,6 +322,15 @@ void handle_trap(rt_ubase_t scause, rt_ubase_t stval, rt_ubase_t sepc,
         tick_isr();
         rt_interrupt_leave();
     }
+#ifdef RT_USING_SMP
+    else if ((SCAUSE_INTERRUPT | SCAUSE_S_SOFTWARE_INTR) == scause)
+    {
+        /* supervisor software interrupt for ipi */
+        rt_interrupt_enter();
+        rt_hw_ipi_handler();
+        rt_interrupt_leave();
+    }
+#endif /* RT_USING_SMP */
     else
     {
         if (SCAUSE_INTERRUPT & scause)

libcpu/risc-v/virt64/interrupt.c

@@ -16,6 +16,10 @@
 #include "interrupt.h"
 
 struct rt_irq_desc irq_desc[MAX_HANDLERS];
+#ifdef RT_USING_SMP
+struct rt_irq_desc ipi_desc[RT_MAX_IPI];
+uint8_t ipi_vectors[RT_CPUS_NR] = {0};
+#endif
 
 static rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
 {
@@ -94,6 +98,16 @@ void rt_hw_interrupt_init()
 }
 
 #ifdef RT_USING_SMP
+void rt_hw_interrupt_set_priority(int vector, unsigned int priority)
+{
+    plic_set_priority(vector, priority);
+}
+
+unsigned int rt_hw_interrupt_get_priority(int vector)
+{
+    return (*(uint32_t *)PLIC_PRIORITY(vector));
+}
+
 rt_bool_t rt_hw_interrupt_is_disabled(void)
 {
     /* Determine the interrupt enable state */
@@ -104,57 +118,109 @@ rt_bool_t rt_hw_interrupt_is_disabled(void)
 
 void rt_hw_spin_lock_init(rt_hw_spinlock_t *_lock)
 {
-    // union rt_hw_spinlock_t *lock = (void *)_lock;
-    // _lock->slock = 0;
+    union rt_hw_spinlock_t *lock = (void *)_lock;
+    _lock->slock = 0;
 }
 
 void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
 {
-    // /* Use ticket lock implemented on top of the 32/64-bit atomic AMO ops.
-    //  * The combined word layout (slock) maps two uint16_t fields:
-    //  *   low 16 bits: owner
-    //  *   high 16 bits: next (ticket allocator)
-    //  * We atomically increment the "next" field by (1 << 16) and use the
-    //  * returned old value to compute our ticket. Then wait until owner == ticket.
-    //  */
-    // rt_atomic_t prev;
-    // rt_atomic_t ticket;
-    // rt_atomic_t owner;
-
-    // /* Allocate a ticket by adding (1 << 16) to slock, prev holds previous value */
-    // prev = rt_hw_atomic_add((volatile rt_atomic_t *)&lock->slock, (rt_atomic_t)(1UL << 16));
-    // ticket = (prev >> 16) & 0xffffUL;
-
-    // /* Wait until owner equals our ticket */
-    // for (;;)
-    // {
-    //     owner = rt_hw_atomic_load((volatile rt_atomic_t *)&lock->slock) & 0xffffUL;
-    //     if (owner == ticket)
-    //         break;
-    //     /* TODO: low-power wait for interrupt while spinning */
-    //     // __asm__ volatile("wfi" ::: "memory");
-    // }
-
-    // /* Ensure all following memory accesses are ordered after acquiring the lock */
-    // __asm__ volatile("fence rw, rw" ::: "memory");
+    /* Use ticket lock implemented on top of the 32/64-bit atomic AMO ops.
+     * The combined word layout (slock) maps two uint16_t fields:
+     *   low 16 bits: owner
+     *   high 16 bits: next (ticket allocator)
+     * We atomically increment the "next" field by (1 << 16) and use the
+     * returned old value to compute our ticket. Then wait until owner == ticket.
+     */
+    rt_atomic_t prev;
+    rt_atomic_t ticket;
+    rt_atomic_t owner;
+
+    /* Allocate a ticket by adding (1 << 16) to slock, prev holds previous value */
+    prev = rt_hw_atomic_add((volatile rt_atomic_t *)&lock->slock, (rt_atomic_t)(1UL << 16));
+    ticket = (prev >> 16) & 0xffffUL;
+
+    /* Wait until owner equals our ticket */
+    for (;;)
+    {
+        owner = rt_hw_atomic_load((volatile rt_atomic_t *)&lock->slock) & 0xffffUL;
+        if (owner == ticket)
+            break;
+        /* TODO: low-power wait for interrupt while spinning */
+        // __asm__ volatile("wfi" ::: "memory");
+    }
+
+    /* Ensure all following memory accesses are ordered after acquiring the lock */
+    __asm__ volatile("fence rw, rw" ::: "memory");
 }
 
 void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
 {
-    // /* Ensure memory operations before unlock are visible before owner increment */
-    // __asm__ volatile("fence rw, rw" ::: "memory");
+    /* Ensure memory operations before unlock are visible before owner increment */
+    __asm__ volatile("fence rw, rw" ::: "memory");
 
-    // /* Increment owner (low 16 bits) to hand over lock to next ticket */
-    // rt_hw_atomic_add((volatile rt_atomic_t *)&lock->slock, (rt_atomic_t)1);
+    /* Increment owner (low 16 bits) to hand over lock to next ticket */
+    rt_hw_atomic_add((volatile rt_atomic_t *)&lock->slock, (rt_atomic_t)1);
 
-    // // TODO: IPI interrupt to wake up other harts waiting for the lock
+    // TODO: IPI interrupt to wake up other harts waiting for the lock
 
-    // /* Make the increment visible to other harts */
-    // __asm__ volatile("fence rw, rw" ::: "memory");
+    /* Make the increment visible to other harts */
+    __asm__ volatile("fence rw, rw" ::: "memory");
 }
 
 void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
 {
-    
+    int cpuid = cpu_mask & -cpu_mask; // get the lowest set bit
+    ipi_vectors[cpuid] |= (uint8_t)ipi_vector;
+    sbi_send_ipi((const unsigned long *)&cpu_mask);
+}
+
+void rt_hw_ipi_init(void)
+{
+    int idx = 0, cpuid = rt_cpu_get_id();
+    ipi_vectors[cpuid] = 0;
+    /* init exceptions table */
+    for (idx = 0; idx < RT_MAX_IPI; idx++)
+    {
+        ipi_desc[idx].handler = RT_NULL;
+        ipi_desc[idx].param = RT_NULL;
+        #ifdef RT_USING_INTERRUPT_INFO
+            rt_snprintf(ipi_desc[idx].name, RT_NAME_MAX - 1, "default");
+            ipi_desc[idx].counter = 0;
+        #endif
+    }
+    set_csr(sie, SIP_SSIP);
+}
+
+void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
+{
+    if(ipi_vector < RT_MAX_IPI)
+    {
+        if (ipi_isr_handler != RT_NULL)
+        {
+            ipi_desc[ipi_vector].handler = (rt_isr_handler_t)ipi_isr_handler;
+            ipi_desc[ipi_vector].param = RT_NULL;
+        }
+    }
+}
+
+void rt_hw_ipi_handler(void)
+{
+    rt_uint32_t ipi_vector;
+
+    ipi_vector = ipi_vectors[rt_cpu_get_id()];
+    while (ipi_vector)
+    {
+        int bitpos = __builtin_ctz(ipi_vector);
+        ipi_vector &= ~(1 << bitpos);
+        if (bitpos < RT_MAX_IPI && ipi_desc[bitpos].handler != RT_NULL)
+        {
+            /* call the irq service routine */
+            ipi_desc[bitpos].handler(bitpos, ipi_desc[bitpos].param);
+        }
+    }
+    ipi_vectors[rt_cpu_get_id()] = 0;
+
+    // clear software interrupt pending bit
+    clear_csr(sip, SIP_SSIP);
 }
 #endif /* RT_USING_SMP */