[libcpu-riscv]: [common64 virt64]:Fix compilation errors after enabling the SMP architecture.

Currently, the bsp: qemu-virt64-riscv does not support the SMP architecture,
and some necessary interfaces are not implemented.

Solution: Add the interface declarations to make the compilation pass.

Signed-off-by: Mengchen Teng <teng_mengchen@163.com>

Author: Tm-C-mT

libcpu/risc-v/common64/cpuport.c

@@ -137,3 +137,15 @@ void rt_hw_set_process_id(int pid)
 {
     // TODO
 }
+
+#ifdef RT_USING_SMP
+void rt_hw_secondary_cpu_up(void)
+{
+    
+}
+
+void secondary_cpu_entry(void)
+{
+
+}
+#endif /* RT_USING_SMP */

libcpu/risc-v/common64/interrupt_gcc.S

@@ -88,6 +88,7 @@ _resume_kernel:
     csrw    sscratch, zero
     sret
 
+#ifndef RT_USING_SMP
 .global rt_hw_interrupt_enable
 rt_hw_interrupt_enable:
     csrs sstatus, a0    /* restore to old csr */
@@ -97,3 +98,18 @@ rt_hw_interrupt_enable:
 rt_hw_interrupt_disable:
     csrrci a0, sstatus, 2   /* clear SIE */
     jr ra
+#else
+.global rt_hw_local_irq_disable
+rt_hw_local_irq_disable:
+    csrrci a0, sstatus, 2
+    jr ra
+
+.global rt_hw_local_irq_enable
+rt_hw_local_irq_enable:
+    csrs sstatus, a0
+    jr ra
+
+.global rt_hw_secondary_cpu_idle_exec
+rt_hw_secondary_cpu_idle_exec:
+    jr ra
+#endif  /* RT_USING_SMP */

libcpu/risc-v/common64/trap.c

@@ -136,6 +136,14 @@ static volatile int nested = 0;
 #define EXIT_TRAP  nested -= 1
 #define CHECK_NESTED_PANIC(cause, tval, epc, eframe) \
     if (nested != 1) handle_nested_trap_panic(cause, tval, epc, eframe)
+#else
+/* Add trap nesting detection under the SMP architecture. */
+static volatile int nested[RT_CPUS_NR] = {0};
+#define ENTER_TRAP nested[rt_hw_cpu_id()] += 1
+#define EXIT_TRAP nested[rt_hw_cpu_id()] -= 1
+#define CHECK_NESTED_PANIC(cause, tval, epc, eframe) \
+    if (nested[rt_hw_cpu_id()] != 1) \
+        handle_nested_trap_panic(cause, tval, epc, eframe)
 #endif /* RT_USING_SMP */
 
 static const char *get_exception_msg(int id)

libcpu/risc-v/virt64/interrupt.c

@@ -92,3 +92,25 @@ void rt_hw_interrupt_init()
 
     plic_set_threshold(0);
 }
+
+#ifdef RT_USING_SMP
+void rt_hw_spin_lock_init(rt_hw_spinlock_t *_lock)
+{
+    
+}
+
+void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
+{
+    
+}
+
+void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
+{
+    
+}
+
+void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
+{
+    
+}
+#endif /* RT_USING_SMP */