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Revert "[RISCV] Cost bf16/f16 vector non-unit memory accesses as legal without zvfhmin/zvfbfmin (llvm#150882)"
This reverts commit fe4f6c1, but leaves the tests that were added. The original commit mistakenly assumed that if regular bf16/f16 loads and stores could be lowered without zvfbfmin/zvfhmin, then so too could masked loads/stores and gathers/scatters. However SelectionDAG can't actually type-legalize masked.load/stores since it needs to be done in ScalarizeMaskedMemIntrinPass. This was causing crashes on IREE because we now returned true for isLegalMaskedLoadStore. The original intent of this was to remove a discrepancy in the loop vectorizer tests whenever predication was enabled, but this has gone away after 92d0924. So I don't think we need to reapply this patch.
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-30
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5 files changed

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-30
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 1 addition & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -2739,27 +2739,6 @@ bool RISCVTargetLowering::isLegalElementTypeForRVV(EVT ScalarTy) const {
27392739
}
27402740
}
27412741

2742-
bool RISCVTargetLowering::isLegalLoadStoreElementTypeForRVV(
2743-
EVT ScalarTy) const {
2744-
if (!ScalarTy.isSimple())
2745-
return false;
2746-
switch (ScalarTy.getSimpleVT().SimpleTy) {
2747-
case MVT::iPTR:
2748-
return Subtarget.is64Bit() ? Subtarget.hasVInstructionsI64() : true;
2749-
case MVT::i8:
2750-
case MVT::i16:
2751-
case MVT::i32:
2752-
case MVT::f16:
2753-
case MVT::bf16:
2754-
case MVT::f32:
2755-
return true;
2756-
case MVT::i64:
2757-
case MVT::f64:
2758-
return Subtarget.hasVInstructionsI64();
2759-
default:
2760-
return false;
2761-
}
2762-
}
27632742

27642743
unsigned RISCVTargetLowering::combineRepeatedFPDivisors() const {
27652744
return NumRepeatedDivisors;
@@ -24369,7 +24348,7 @@ bool RISCVTargetLowering::isLegalStridedLoadStore(EVT DataType,
2436924348
return false;
2437024349

2437124350
EVT ScalarType = DataType.getScalarType();
24372-
if (!isLegalLoadStoreElementTypeForRVV(ScalarType))
24351+
if (!isLegalElementTypeForRVV(ScalarType))
2437324352
return false;
2437424353

2437524354
if (!Subtarget.enableUnalignedVectorMem() &&

‎llvm/lib/Target/RISCV/RISCVISelLowering.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -384,7 +384,6 @@ class RISCVTargetLowering : public TargetLowering {
384384
bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override;
385385

386386
bool isLegalElementTypeForRVV(EVT ScalarTy) const;
387-
bool isLegalLoadStoreElementTypeForRVV(EVT ScalarTy) const;
388387

389388
bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
390389

‎llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ bool RISCVTargetLowering::isLegalInterleavedAccessType(
3232
if (!isTypeLegal(VT))
3333
return false;
3434

35-
if (!isLegalLoadStoreElementTypeForRVV(VT.getScalarType()) ||
35+
if (!isLegalElementTypeForRVV(VT.getScalarType()) ||
3636
!allowsMemoryAccessForAlignment(VTy->getContext(), DL, VT, AddrSpace,
3737
Alignment))
3838
return false;

‎llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -265,7 +265,7 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
265265
if (!ST->enableUnalignedVectorMem() && Alignment < ElemType.getStoreSize())
266266
return false;
267267

268-
return TLI->isLegalLoadStoreElementTypeForRVV(ElemType);
268+
return TLI->isLegalElementTypeForRVV(ElemType);
269269
}
270270

271271
bool isLegalMaskedLoad(Type *DataType, Align Alignment,
@@ -297,7 +297,7 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
297297
if (!ST->enableUnalignedVectorMem() && Alignment < ElemType.getStoreSize())
298298
return false;
299299

300-
return TLI->isLegalLoadStoreElementTypeForRVV(ElemType);
300+
return TLI->isLegalElementTypeForRVV(ElemType);
301301
}
302302

303303
bool isLegalMaskedGather(Type *DataType, Align Alignment) const override {

‎llvm/test/Analysis/CostModel/RISCV/masked_ldst.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -13,14 +13,14 @@ define void @fixed() {
1313
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i32 = call <2 x i32> @llvm.masked.load.v2i32.p0(ptr undef, i32 8, <2 x i1> undef, <2 x i32> undef)
1414
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4i32 = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr undef, i32 8, <4 x i1> undef, <4 x i32> undef)
1515
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2i64 = call <2 x i64> @llvm.masked.load.v2i64.p0(ptr undef, i32 8, <2 x i1> undef, <2 x i64> undef)
16-
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v2f16 = call <2 x half> @llvm.masked.load.v2f16.p0(ptr undef, i32 8, <2 x i1> undef, <2 x half> undef)
17-
; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %v4f16 = call <4 x half> @llvm.masked.load.v4f16.p0(ptr undef, i32 8, <4 x i1> undef, <4 x half> undef)
18-
; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %v8f16 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr undef, i32 8, <8 x i1> undef, <8 x half> undef)
16+
; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %v2f16 = call <2 x half> @llvm.masked.load.v2f16.p0(ptr undef, i32 8, <2 x i1> undef, <2 x half> undef)
17+
; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %v4f16 = call <4 x half> @llvm.masked.load.v4f16.p0(ptr undef, i32 8, <4 x i1> undef, <4 x half> undef)
18+
; CHECK-NEXT: Cost Model: Found an estimated cost of 39 for instruction: %v8f16 = call <8 x half> @llvm.masked.load.v8f16.p0(ptr undef, i32 8, <8 x i1> undef, <8 x half> undef)
1919
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f32 = call <2 x float> @llvm.masked.load.v2f32.p0(ptr undef, i32 8, <2 x i1> undef, <2 x float> undef)
2020
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v4f32 = call <4 x float> @llvm.masked.load.v4f32.p0(ptr undef, i32 8, <4 x i1> undef, <4 x float> undef)
2121
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %v2f64 = call <2 x double> @llvm.masked.load.v2f64.p0(ptr undef, i32 8, <2 x i1> undef, <2 x double> undef)
2222
; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v4i64 = call <4 x i64> @llvm.masked.load.v4i64.p0(ptr undef, i32 8, <4 x i1> undef, <4 x i64> undef)
23-
; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %v32f16 = call <32 x half> @llvm.masked.load.v32f16.p0(ptr undef, i32 8, <32 x i1> undef, <32 x half> undef)
23+
; CHECK-NEXT: Cost Model: Found an estimated cost of 223 for instruction: %v32f16 = call <32 x half> @llvm.masked.load.v32f16.p0(ptr undef, i32 8, <32 x i1> undef, <32 x half> undef)
2424
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
2525
;
2626
entry:

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