Reg supports intrinsic write method.

Author: shtaxxx

tests/extension/thread_/stream_reg/thread_stream_reg.py

@@ -29,7 +29,7 @@ def mkLed():
 
     # to extern
 
-    when = a < 4
+    when = a > 4
     r = strm.Reg(a, when)
 
     # from extern
@@ -40,14 +40,16 @@ def mkLed():
     def comp_stream(size, offset):
         strm.set_source('a', ram_a, offset, size)
         strm.set_sink('b', ram_b, offset, size)
+        # set Reg value
+        r.write(1000)
         strm.run()
         strm.join()
 
     def comp_sequential(size, offset):
-        r = 0
+        r = 1000
         for i in range(size):
             a = ram_a.read(i + offset)
-            if a < 4:
+            if a > 4:
                 r = a
             b = r + 100
             ram_b.write(i + offset, b)

veriloggen/stream/stypes.py

@@ -3172,6 +3172,7 @@ def _implement(self, m, seq, svalid=None, senable=None):
 
 
 class Reg(_SpecialOperator):
+    __intrinsics__ = ('write')
     latency = 1
 
     def __init__(self, data, when=None):
@@ -3207,6 +3208,13 @@ def _implement(self, m, seq, svalid=None, senable=None):
 
         seq(data(arg_data[0]), cond=enable)
 
+    def write(self, fsm, value):
+        cond = fsm.here
+
+        self.seq.If(cond)(
+            self.sig_data(value)
+        )
+
 
 class ReadRAM(_SpecialOperator):
     latency = 3