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Samples are updated.
1 parent 735c33c commit f51cb30

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3 files changed

+22
-22
lines changed

3 files changed

+22
-22
lines changed

README.md

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -71,15 +71,15 @@ def mkLed():
7171
count = m.Reg('count', 32)
7272

7373
m.Always(Posedge(clk),
74-
[ If(rst,
75-
[ count.set(0) ],
76-
[ count.set(count + 1) ])])
74+
( If(rst,
75+
( count.set(0), ),
76+
( count.set(count + 1), )), ))
7777

7878
m.Always(Posedge(clk),
79-
[ If(rst,
80-
[ led.set(0) ],
81-
[ If(count == 1024 - 1,
82-
[ led.set(led + 1) ])])])
79+
( If(rst,
80+
( led.set(0), ),
81+
( If(count == 1024 - 1,
82+
( led.set(led + 1), )))), ))
8383

8484
return m
8585

sample/bram/bram.py

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -60,14 +60,14 @@ def goto_next():
6060
return state.set( state + 1 )
6161

6262
m.Always(Posedge(clk),
63-
[ If(rst,
64-
[ addr.set(0), datain.set(0), write.set(0), state.set(0) ],
65-
[ If(cond(), [ addr.set(0), datain.set(0), write.set(0), goto_next() ]),
66-
If(cond(), [ write.set(1), datain.set(datain + 4), goto_next() ]),
67-
If(cond(), [ write.set(0), goto_next() ]),
68-
If(cond(), [ If(addr == 128,
69-
[ addr.set(0), state.set(label[0]) ],
70-
[ addr.set(addr + 1), state.set(label[1]) ])])])])
63+
( If(rst,
64+
( addr.set(0), datain.set(0), write.set(0), state.set(0) ),
65+
( If(cond(), ( addr.set(0), datain.set(0), write.set(0), goto_next() )),
66+
If(cond(), ( write.set(1), datain.set(datain + 4), goto_next() )),
67+
If(cond(), ( write.set(0), goto_next() )),
68+
If(cond(), ( If(addr == 128,
69+
( addr.set(0), state.set(label[0]) ),
70+
( addr.set(addr + 1), state.set(label[1]) ))))))))
7171
return m
7272

7373
#-------------------------------------------------------------------------------

sample/led/led.py

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -13,15 +13,15 @@ def mkLed():
1313
count = m.Reg('count', 32)
1414

1515
m.Always(Posedge(clk),
16-
[ If(rst,
17-
[ count.set(0) ],
18-
[ count.set(count + 1) ])])
16+
( If(rst,
17+
( count.set(0), ),
18+
( count.set(count + 1), )), ))
1919

2020
m.Always(Posedge(clk),
21-
[ If(rst,
22-
[ led.set(0) ],
23-
[ If(count == 1024 - 1,
24-
[ led.set(led + 1) ])])])
21+
( If(rst,
22+
( led.set(0), ),
23+
( If(count == 1024 - 1,
24+
( led.set(led + 1), )))), ))
2525

2626
return m
2727

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