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ValueError is raised when multiple definition is detected. New tests for checking multiple definitions are added
1 parent 7003164 commit f2ac251

22 files changed

+757
-45
lines changed

‎tests/core/generate/Makefile‎

Lines changed: 6 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,29 +1,18 @@
1-
TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
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ARGS=
3-
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PYTHON=python3
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#PYTHON=python
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#OPT=-m pdb
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#OPT=-m cProfile -s time
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#OPT=-m cProfile -o profile.rslt
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.PHONY: all
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all: test
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.PHONY: run
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run:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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all: clean
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.PHONY: test
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test:
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$(PYTHON) -m pytest -vv
2010

21-
.PHONY: check
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check:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
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iverilog -tnull -Wall tmp.v
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rm -f tmp.v
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.PHONY: run
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run:
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find . -maxdepth 1 -type d | grep "./" | xargs -I {} make run -C {}
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2715
.PHONY: clean
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clean:
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rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd
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rm -rf *.pyc __pycache__ parsetab.py *.out .cache
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find . -maxdepth 1 -type d | grep "./" | xargs -I {} make clean -C {}

‎tests/core/generate/instance/Makefile‎

Lines changed: 29 additions & 0 deletions
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TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
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ARGS=
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PYTHON=python3
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#PYTHON=python
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#OPT=-m pdb
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#OPT=-m cProfile -s time
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#OPT=-m cProfile -o profile.rslt
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.PHONY: all
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all: test
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.PHONY: run
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run:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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.PHONY: test
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test:
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$(PYTHON) -m pytest -vv
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.PHONY: check
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check:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
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iverilog -tnull -Wall tmp.v
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rm -f tmp.v
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27+
.PHONY: clean
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clean:
29+
rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd

‎tests/core/generate/instance/generate_instance.py‎

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,54 @@
1+
from __future__ import absolute_import
2+
from __future__ import print_function
3+
import sys
4+
import os
5+
6+
# the next line can be removed after installation
7+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
8+
9+
from veriloggen import *
10+
11+
def mkSubmod():
12+
m = Module('submod')
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pos = m.Parameter('POS', 0)
14+
clk = m.Input('CLK')
15+
rst = m.Input('RST')
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led = m.Output('LED')
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count = m.Reg('count', 32)
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m.Always(Posedge(clk))(
19+
If(rst)(
20+
count(0)
21+
).Else(
22+
If(count == 1023)(
23+
count(0)
24+
).Else(
25+
count(count + 1)
26+
)
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))
28+
m.Assign( led(count[pos]) )
29+
return m
30+
31+
def mkLed():
32+
m = Module('blinkled')
33+
width = m.Parameter('WIDTH', 8)
34+
clk = m.Input('CLK')
35+
rst = m.Input('RST')
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led = m.Output('LED', width)
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38+
# genvar i;
39+
i = m.Genvar('i')
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41+
# generate for(i=0; i<WIDTH; i=i+1) begin: gen_for;
42+
gen_for = m.GenerateFor(i(0), i<width, i(i+1), scope='gen_for')
43+
submod = mkSubmod()
44+
params = [ ('POS', i+2) ]
45+
ports = [ ('CLK', clk), ('RST', rst), ('LED', led[i]) ]
46+
gen_for.Instance(submod, 'inst_submod', params, ports)
47+
# ... end endgenerate
48+
49+
return m
50+
51+
if __name__ == '__main__':
52+
led = mkLed()
53+
verilog = led.to_verilog()
54+
print(verilog)

‎tests/core/generate/instance/test_generate_instance.py‎

Lines changed: 60 additions & 0 deletions
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1+
from __future__ import absolute_import
2+
from __future__ import print_function
3+
import generate_instance
4+
5+
expected_verilog = """
6+
module blinkled #
7+
(
8+
parameter WIDTH = 8
9+
)
10+
(
11+
input CLK,
12+
input RST,
13+
output [WIDTH-1:0] LED
14+
);
15+
16+
genvar i;
17+
generate for(i=0; i<WIDTH; i=i+1) begin: gen_for
18+
submod # ( .POS(i+2) )
19+
inst_submod ( .CLK(CLK), .RST(RST), .LED(LED[i]) );
20+
end endgenerate
21+
22+
endmodule
23+
24+
module submod #
25+
(
26+
parameter POS = 0
27+
)
28+
(
29+
input CLK,
30+
input RST,
31+
output LED
32+
);
33+
reg [32-1:0] count;
34+
always @(posedge CLK) begin
35+
if(RST) begin
36+
count <= 0;
37+
end else begin
38+
if(count == 1023) begin
39+
count <= 0;
40+
end else begin
41+
count <= count + 1;
42+
end
43+
end
44+
end
45+
assign LED = count[POS];
46+
endmodule
47+
"""
48+
49+
def test():
50+
test_module = generate_instance.mkLed()
51+
code = test_module.to_verilog()
52+
53+
from pyverilog.vparser.parser import VerilogParser
54+
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
55+
parser = VerilogParser()
56+
expected_ast = parser.parse(expected_verilog)
57+
codegen = ASTCodeGenerator()
58+
expected_code = codegen.visit(expected_ast)
59+
60+
assert(expected_code == code)

‎tests/core/generate/variable/Makefile‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
2+
ARGS=
3+
4+
PYTHON=python3
5+
#PYTHON=python
6+
#OPT=-m pdb
7+
#OPT=-m cProfile -s time
8+
#OPT=-m cProfile -o profile.rslt
9+
10+
.PHONY: all
11+
all: test
12+
13+
.PHONY: run
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run:
15+
$(PYTHON) $(OPT) $(TARGET) $(ARGS)
16+
17+
.PHONY: test
18+
test:
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$(PYTHON) -m pytest -vv
20+
21+
.PHONY: check
22+
check:
23+
$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
24+
iverilog -tnull -Wall tmp.v
25+
rm -f tmp.v
26+
27+
.PHONY: clean
28+
clean:
29+
rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd

‎tests/core/generate/generate.py‎ renamed to ‎tests/core/generate/variable/generate_variable.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
import os
55

66
# the next line can be removed after installation
7-
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
7+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
88

99
from veriloggen import *
1010

‎tests/core/generate/test_generate.py‎ renamed to ‎tests/core/generate/variable/test_generate_variable.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
from __future__ import absolute_import
22
from __future__ import print_function
3-
import generate
3+
import generate_variable
44

55
expected_verilog = """
66
module blinkled #
@@ -57,7 +57,7 @@
5757
"""
5858

5959
def test():
60-
test_module = generate.mkLed()
60+
test_module = generate_variable.mkLed()
6161
code = test_module.to_verilog()
6262

6363
from pyverilog.vparser.parser import VerilogParser

‎tests/core/multiple_definition/Makefile‎

Lines changed: 18 additions & 0 deletions
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PYTHON=python3
2+
#PYTHON=python
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.PHONY: all
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all: clean
6+
7+
.PHONY: test
8+
test:
9+
$(PYTHON) -m pytest -vv
10+
11+
.PHONY: run
12+
run:
13+
find . -maxdepth 1 -type d | grep "./" | xargs -I {} make run -C {}
14+
15+
.PHONY: clean
16+
clean:
17+
rm -rf *.pyc __pycache__ parsetab.py *.out .cache
18+
find . -maxdepth 1 -type d | grep "./" | xargs -I {} make clean -C {}

‎tests/core/multiple_definition/instance/Makefile‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
2+
ARGS=
3+
4+
PYTHON=python3
5+
#PYTHON=python
6+
#OPT=-m pdb
7+
#OPT=-m cProfile -s time
8+
#OPT=-m cProfile -o profile.rslt
9+
10+
.PHONY: all
11+
all: test
12+
13+
.PHONY: run
14+
run:
15+
$(PYTHON) $(OPT) $(TARGET) $(ARGS)
16+
17+
.PHONY: test
18+
test:
19+
$(PYTHON) -m pytest -vv
20+
21+
.PHONY: check
22+
check:
23+
$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
24+
iverilog -tnull -Wall tmp.v
25+
rm -f tmp.v
26+
27+
.PHONY: clean
28+
clean:
29+
rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd

‎tests/core/multiple_definition/instance/multiple_definition_instance.py‎

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,64 @@
1+
from __future__ import absolute_import
2+
from __future__ import print_function
3+
import sys
4+
import os
5+
6+
# the next line can be removed after installation
7+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
8+
9+
from veriloggen import *
10+
11+
def mkSub():
12+
m = Module('blinkled')
13+
clk = m.Input('CLK')
14+
rst = m.Input('RST')
15+
count = m.OutputReg('count', 32)
16+
m.Always(Posedge(clk))(
17+
If(rst)(
18+
count(0)
19+
).Else(
20+
If(count == 1023)(
21+
count(0)
22+
).Else(
23+
count(count + 1)
24+
)
25+
))
26+
return m
27+
28+
def mkLed():
29+
m = Module('blinkled')
30+
width = m.Parameter('WIDTH', 8)
31+
clk = m.Input('CLK')
32+
rst = m.Input('RST')
33+
led = m.OutputReg('LED', width)
34+
count = m.Wire('count', 32)
35+
36+
sub = mkSub()
37+
m.Instance(sub, 'inst_sub', m.connect_params(sub), m.connect_ports(sub))
38+
39+
# by multiple definition, throws an exception here
40+
m.Instance(sub, 'inst_sub', m.connect_params(sub), m.connect_ports(sub))
41+
42+
m.Always(Posedge(clk))(
43+
If(rst)(
44+
led(0)
45+
).Else(
46+
If(count == 1023)(
47+
led(led + 1)
48+
)
49+
))
50+
51+
return m
52+
53+
if __name__ == '__main__':
54+
try:
55+
led = mkLed()
56+
except ValueError as e:
57+
print(e.args[0])
58+
print('But it was detected')
59+
sys.exit()
60+
61+
raise ValueError("Multiple definition was not detected.")
62+
63+
#verilog = led.to_verilog()
64+
#print(verilog)

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