Merge branch 'fix_read_ram_error_check' into develop

Author: shtaxxx

veriloggen/stream/stypes.py

@@ -3493,10 +3493,10 @@ def _implement(self, m, seq, svalid=None, senable=None):
                              (self.latency, 2))
 
         if len(self.args) == 3 and self.latency == 2:
-            raise ValueError('Output register is required for when option')
+            raise ValueError('latency = 2 is not allowed, if when option is used.')
 
-        if senable is not None:
-            raise NotImplementedError('senable is not supported.')
+        if senable is not None and self.latency == 2:
+            raise NotImplementedError('senable is not supported, if when option is used.')
 
         datawidth = self.bit_length()
         signed = self.get_signed()