Merge branch 'feature_optimize_axim' into develop

Author: shtaxxx

tests/extension/thread_/multibank_nested_ram_dma_block/thread_multibank_nested_ram_dma_block.py

@@ -34,6 +34,8 @@ def mkLed(memory_datawidth=128):
     array_len = 128
     array_size = (array_len + array_len) * 4 * numbanks
 
+    laddr_offset = 32
+
     def blink(size):
         all_ok.value = True
 
@@ -53,7 +55,7 @@ def blink(size):
     def body(size, offset):
         # write
         count = 0
-        blk_offset = 0
+        blk_offset = laddr_offset
         bias = 0
         done = False
         while count < size:
@@ -70,14 +72,14 @@ def body(size, offset):
                 bias += block_size
             blk_offset += block_size
 
-        laddr = 0
+        laddr = laddr_offset
         gaddr = offset
         myaxi.dma_write_block(myram, laddr, gaddr, size, block_size)
         print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
 
         # write
         count = 0
-        blk_offset = 0
+        blk_offset = laddr_offset
         bias = 0
         done = False
         while count < size:
@@ -94,19 +96,19 @@ def body(size, offset):
                 bias += block_size
             blk_offset += block_size
 
-        laddr = 0
+        laddr = laddr_offset
         gaddr = array_size + offset
         myaxi.dma_write_block(myram, laddr, gaddr, size, block_size)
         print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
 
         # read
-        laddr = 0
+        laddr = laddr_offset
         gaddr = offset
         myaxi.dma_read_block(myram, laddr, gaddr, size, block_size)
         print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
 
         count = 0
-        blk_offset = 0
+        blk_offset = laddr_offset
         bias = 0
         done = False
         while count < size:
@@ -127,13 +129,13 @@ def body(size, offset):
             blk_offset += block_size
 
         # read
-        laddr = 0
+        laddr = laddr_offset
         gaddr = array_size + offset
         myaxi.dma_read_block(myram, laddr, gaddr, size, block_size)
         print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
 
         count = 0
-        blk_offset = 0
+        blk_offset = laddr_offset
         bias = 0
         done = False
         while count < size:

tests/extension/thread_/multibank_ram_dma_block/thread_multibank_ram_dma_block.py

@@ -35,6 +35,8 @@ def mkLed(memory_datawidth=32):
     array_len = 32
     array_size = (array_len + array_len) * 4 * numbanks
 
+    laddr_offset = 32
+
     def blink(size):
         all_ok.value = True
 
@@ -54,7 +56,7 @@ def blink(size):
     def body(size, offset):
         # write
         count = 0
-        blk_offset = 0
+        blk_offset = laddr_offset
         bias = 0
         done = False
         while count < size:
@@ -71,14 +73,14 @@ def body(size, offset):
                 bias += block_size
             blk_offset += block_size
 
-        laddr = 0
+        laddr = laddr_offset
         gaddr = offset
         myaxi.dma_write_block(myram0, laddr, gaddr, size, block_size)
         print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
 
         # write
         count = 0
-        blk_offset = 0
+        blk_offset = laddr_offset
         bias = 0
         done = False
         while count < size:
@@ -95,19 +97,19 @@ def body(size, offset):
                 bias += block_size
             blk_offset += block_size
 
-        laddr = 0
+        laddr = laddr_offset
         gaddr = array_size + offset
         myaxi.dma_write_block(myram1, laddr, gaddr, size, block_size)
         print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
 
         # read
-        laddr = 0
+        laddr = laddr_offset
         gaddr = offset
         myaxi.dma_read_block(myram1, laddr, gaddr, size, block_size)
         print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
 
         count = 0
-        blk_offset = 0
+        blk_offset = laddr_offset
         bias = 0
         done = False
         while count < size:
@@ -128,13 +130,13 @@ def body(size, offset):
             blk_offset += block_size
 
         # read
-        laddr = 0
+        laddr = laddr_offset
         gaddr = array_size + offset
         myaxi.dma_read_block(myram0, laddr, gaddr, size, block_size)
         print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
 
         count = 0
-        blk_offset = 0
+        blk_offset = laddr_offset
         bias = 0
         done = False
         while count < size:

tests/extension/thread_/multibank_ram_dma_packed/thread_multibank_ram_dma_packed.py

@@ -34,6 +34,8 @@ def mkLed(memory_datawidth=128):
     array_len = 16
     array_size = (array_len + array_len) * 4 * numbanks
 
+    laddr_offset = 32
+
     def blink(size):
         all_ok.value = True
 
@@ -53,50 +55,54 @@ def blink(size):
 
     def body(size, offset):
         # write
+        ram_offset = laddr_offset // numbanks
         for bank in range(numbanks):
             for i in range(size):
                 wdata.value = i + 0x1000 + (bank << 16)
-                myram0.write_bank(bank, i, wdata)
+                myram0.write_bank(bank, ram_offset + i, wdata)
 
-        laddr = 0
+        laddr = laddr_offset
         gaddr = offset
         myaxi.dma_write_packed(myram0, laddr, gaddr, size * numbanks)
         print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
 
         # write
+        ram_offset = laddr_offset // numbanks
         for bank in range(numbanks):
             for i in range(size):
                 wdata.value = i + 0x4000 + (bank << 16)
-                myram1.write_bank(bank, i, wdata)
+                myram1.write_bank(bank, ram_offset + i, wdata)
 
-        laddr = 0
+        laddr = laddr_offset
         gaddr = array_size + offset
         myaxi.dma_write_packed(myram1, laddr, gaddr, size * numbanks)
         print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
 
         # read
-        laddr = 0
+        laddr = laddr_offset
         gaddr = offset
         myaxi.dma_read_packed(myram1, laddr, gaddr, size * numbanks)
         print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
 
+        ram_offset = laddr_offset // numbanks
         for bank in range(numbanks):
             for i in range(size):
-                rdata.value = myram1.read_bank(bank, i)
+                rdata.value = myram1.read_bank(bank, ram_offset + i)
                 rexpected.value = i + 0x1000 + (bank << 16)
                 if vthread.verilog.NotEql(rdata, rexpected):
                     print('rdata[%d:%d] = %d (expected %d)' % (bank, i, rdata, rexpected))
                     all_ok.value = False
 
         # read
-        laddr = 0
+        laddr = laddr_offset
         gaddr = array_size + offset
         myaxi.dma_read_packed(myram0, laddr, gaddr, size * numbanks)
         print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
 
+        ram_offset = laddr_offset // numbanks
         for bank in range(numbanks):
             for i in range(size):
-                rdata.value = myram0.read_bank(bank, i)
+                rdata.value = myram0.read_bank(bank, ram_offset + i)
                 rexpected.value = i + 0x4000 + (bank << 16)
                 if vthread.verilog.NotEql(rdata, rexpected):
                     print('rdata[%d:%d] = %d (expected %d)' % (bank, i, rdata, rexpected))

tests/extension/thread_/multibank_ram_dma_packed_long/thread_multibank_ram_dma_packed_long.py

@@ -34,6 +34,8 @@ def mkLed(memory_datawidth=128):
     array_len = 256 + 128
     array_size = (array_len + array_len) * 4 * numbanks
 
+    laddr_offset = 32
+
     def blink(size):
         all_ok.value = True
 
@@ -49,50 +51,54 @@ def blink(size):
 
     def body(size, offset):
         # write
+        ram_offset = laddr_offset // numbanks
         for bank in range(numbanks):
             for i in range(size):
                 wdata.value = i + 0x1000 + (bank << 16)
-                myram0.write_bank(bank, i, wdata)
+                myram0.write_bank(bank, ram_offset + i, wdata)
 
-        laddr = 0
+        laddr = laddr_offset
         gaddr = offset
         myaxi.dma_write_packed(myram0, laddr, gaddr, size * numbanks)
         print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
 
         # write
+        ram_offset = laddr_offset // numbanks
         for bank in range(numbanks):
             for i in range(size):
                 wdata.value = i + 0x4000 + (bank << 16)
-                myram1.write_bank(bank, i, wdata)
+                myram1.write_bank(bank, ram_offset + i, wdata)
 
-        laddr = 0
+        laddr = laddr_offset
         gaddr = array_size + offset
         myaxi.dma_write_packed(myram1, laddr, gaddr, size * numbanks)
         print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
 
         # read
-        laddr = 0
+        laddr = laddr_offset
         gaddr = offset
         myaxi.dma_read_packed(myram1, laddr, gaddr, size * numbanks)
         print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
 
+        ram_offset = laddr_offset // numbanks
         for bank in range(numbanks):
             for i in range(size):
-                rdata.value = myram1.read_bank(bank, i)
+                rdata.value = myram1.read_bank(bank, ram_offset + i)
                 rexpected.value = i + 0x1000 + (bank << 16)
                 if vthread.verilog.NotEql(rdata, rexpected):
                     print('rdata[%d] = %d (expected %d)' % (i, rdata, rexpected))
                     all_ok.value = False
 
         # read
-        laddr = 0
+        laddr = laddr_offset
         gaddr = array_size + offset
         myaxi.dma_read_packed(myram0, laddr, gaddr, size * numbanks)
         print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
 
+        ram_offset = laddr_offset // numbanks
         for bank in range(numbanks):
             for i in range(size):
-                rdata.value = myram0.read_bank(bank, i)
+                rdata.value = myram0.read_bank(bank, ram_offset + i)
                 rexpected.value = i + 0x4000 + (bank << 16)
                 if vthread.verilog.NotEql(rdata, rexpected):
                     print('rdata[%d] = %d (expected %d)' % (i, rdata, rexpected))

tests/extension/thread_/multibank_ram_dma_packed_narrow/thread_multibank_ram_dma_packed_narrow.py

@@ -34,6 +34,8 @@ def mkLed(memory_datawidth=32):
     array_len = 16
     array_size = (array_len + array_len) * 4 * numbanks
 
+    laddr_offset = 32
+
     def blink(size):
         all_ok.value = True
 
@@ -53,50 +55,54 @@ def blink(size):
 
     def body(size, offset):
         # write
+        ram_offset = laddr_offset // numbanks
         for bank in range(numbanks):
             for i in range(size):
                 wdata.value = i + 0x1000 + (bank << 16)
-                myram0.write_bank(bank, i, wdata)
+                myram0.write_bank(bank, ram_offset + i, wdata)
 
-        laddr = 0
+        laddr = laddr_offset
         gaddr = offset
         myaxi.dma_write_packed(myram0, laddr, gaddr, size * numbanks)
         print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
 
         # write
+        ram_offset = laddr_offset // numbanks
         for bank in range(numbanks):
             for i in range(size):
                 wdata.value = i + 0x4000 + (bank << 16)
-                myram1.write_bank(bank, i, wdata)
+                myram1.write_bank(bank, ram_offset + i, wdata)
 
-        laddr = 0
+        laddr = laddr_offset
         gaddr = array_size + offset
         myaxi.dma_write_packed(myram1, laddr, gaddr, size * numbanks)
         print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
 
         # read
-        laddr = 0
+        laddr = laddr_offset
         gaddr = offset
         myaxi.dma_read_packed(myram1, laddr, gaddr, size * numbanks)
         print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
 
+        ram_offset = laddr_offset // numbanks
         for bank in range(numbanks):
             for i in range(size):
-                rdata.value = myram1.read_bank(bank, i)
+                rdata.value = myram1.read_bank(bank, ram_offset + i)
                 rexpected.value = i + 0x1000 + (bank << 16)
                 if vthread.verilog.NotEql(rdata, rexpected):
                     print('rdata[%d:%d] = %d (expected %d)' % (bank, i, rdata, rexpected))
                     all_ok.value = False
 
         # read
-        laddr = 0
+        laddr = laddr_offset
         gaddr = array_size + offset
         myaxi.dma_read_packed(myram0, laddr, gaddr, size * numbanks)
         print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
 
+        ram_offset = laddr_offset // numbanks
         for bank in range(numbanks):
             for i in range(size):
-                rdata.value = myram0.read_bank(bank, i)
+                rdata.value = myram0.read_bank(bank, ram_offset + i)
                 rexpected.value = i + 0x4000 + (bank << 16)
                 if vthread.verilog.NotEql(rdata, rexpected):
                     print('rdata[%d:%d] = %d (expected %d)' % (bank, i, rdata, rexpected))