Merge branch 'fix_stream_enable' into develop

Author: shtaxxx

tests/extension/stream_/div_validready/test_stream_div_validready.py

@@ -274,7 +274,7 @@
     .CLK(CLK),
     .RST(RST),
     .update(_divide_div_update_2),
-    .enable(1),
+    .enable(1'd1),
     .in_a(_divide_div_abs_ldata_2),
     .in_b(_divide_div_abs_rdata_2),
     .rslt(_divide_div_abs_odata_2)

tests/extension/stream_/substream/test_stream_substream.py

@@ -177,7 +177,7 @@
   wire signed [32-1:0] _times_data_2;
   assign _times_data_2 = _times_mul_odata_reg_2;
   wire _times_mul_update_2;
-  assign _times_mul_update_2 = 1;
+  assign _times_mul_update_2 = 1'd1;
 
   multiplier_0
   _times_mul_2

veriloggen/stream/stypes.py

@@ -620,7 +620,7 @@ def _implement(self, m, seq, svalid=None, senable=None):
         if senable is not None:
             m.Assign(update(senable))
         else:
-            m.Assign(update(1))
+            m.Assign(update(vtypes.Int(1, 1)))
 
         ports = [('CLK', clk), ('update', update),
                  ('a', ldata), ('b', rdata), ('c', odata)]
@@ -715,10 +715,10 @@ def _implement(self, m, seq, svalid=None, senable=None):
         if senable is not None:
             m.Assign(update(senable))
         else:
-            m.Assign(update(1))
+            m.Assign(update(vtypes.Int(1, 1)))
 
         params = [('W_D', width)]
-        ports = [('CLK', clk), ('RST', rst), ('update', update),  ('enable', 1),
+        ports = [('CLK', clk), ('RST', rst), ('update', update),  ('enable', vtypes.Int(1, 1)),
                  ('in_a', abs_ldata), ('in_b', abs_rdata), ('rslt', abs_odata)]
 
         m.Instance(inst, self.name('div'), params, ports)
@@ -807,10 +807,10 @@ def _implement(self, m, seq, svalid=None, senable=None):
         if senable is not None:
             m.Assign(update(senable))
         else:
-            m.Assign(update(1))
+            m.Assign(update(vtypes.Int(1, 1)))
 
         params = [('W_D', width)]
-        ports = [('CLK', clk), ('RST', rst), ('update', update), ('enable', 1),
+        ports = [('CLK', clk), ('RST', rst), ('update', update), ('enable', vtypes.Int(1, 1)),
                  ('in_a', abs_ldata), ('in_b', abs_rdata), ('mod', abs_odata)]
 
         m.Instance(inst, self.name('div'), params, ports)
@@ -1804,7 +1804,7 @@ def _implement(self, m, seq, svalid=None, senable=None):
         if senable is not None:
             m.Assign(update(senable))
         else:
-            m.Assign(update(1))
+            m.Assign(update(vtypes.Int(1, 1)))
 
         ports = [('CLK', clk), ('update', update),
                  ('a', adata), ('b', bdata), ('c', cdata), ('d', odata)]