vthread.RAM can accept RAW value representation in str.

Author: shtaxxx

veriloggen/core/vtypes.py

@@ -720,9 +720,20 @@ def bit_length(self):
 
 class Int(_Constant):
 
-    def __init__(self, value, width=None, base=None, signed=False):
+    def __init__(self, value, width=None, base=None, signed=False, is_raw_value=False):
         _Constant.__init__(self, value, width, base)
-        if isinstance(value, int):
+        if is_raw_value:
+            if width is None:
+                raise ValueError(
+                    'width is required when is_raw_value is enabled.')
+            if base is None:
+                raise ValueError(
+                    'base is required when is_raw_value is enabled.')
+            self.value = value
+            self.width = width
+            self.base = base
+            self.signed = signed
+        elif isinstance(value, int):
             self.value = value
             self.width = width
             self.base = base

veriloggen/types/ram.py

@@ -30,13 +30,21 @@ def mkRAMDefinition(name, datawidth=32, addrwidth=10, numports=2,
                             str(type(initvals)))
 
         new_initvals = []
+        base = 16
         for initval in initvals:
             if isinstance(initval, int):
                 new_initvals.append(vtypes.Int(initval, datawidth, base=16))
-            elif isinstance(initval, vtypes.Int):
+            elif isinstance(initval, vtypes.Int) and isinstance(initval.value, int):
                 v = copy.deepcopy(initval)
                 v.width = datawidth
-                v.base = 16
+                v.base = base
+                new_initvals.append(v)
+            elif isinstance(initval, vtypes.Int) and isinstance(initval.value, str):
+                v = copy.deepcopy(initval)
+                v.width = datawidth
+                if v.base != 2 and v.base != 16:
+                    raise ValueError('base must be 2 or 16')
+                base = v.base
                 new_initvals.append(v)
             else:
                 raise TypeError("values of initvals must be int, not '%s" %
@@ -46,7 +54,7 @@ def mkRAMDefinition(name, datawidth=32, addrwidth=10, numports=2,
 
         if 2 ** addrwidth > len(initvals):
             initvals.extend(
-                [vtypes.Int(0, datawidth, base=16)
+                [vtypes.Int(0, datawidth, base=base)
                  for _ in range(2 ** addrwidth - len(initvals))])
 
         m.Initial(