updated for the updated ipgen

shtaxxx · shtaxxx · commit e4282a3b1052 · 2017-10-07T12:54:26.000+09:00
diff --git a/examples/thread_embedded_verilog_ipcore/Makefile b/examples/thread_embedded_verilog_ipcore/Makefile
@@ -13,7 +13,7 @@ all: test
 .PHONY: run
 run:
 	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
-	make compile run -C ipgen_*_v1_00_a/test/
+	make compile run -C *_v1_00_a/test/
 
 .PHONY: test
 test:
@@ -28,4 +28,4 @@ check:
 .PHONY: clean
 clean:
 	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd 
-	rm -rf ipgen_*_v1_00_a
+	rm -rf *_v1_00_a
diff --git a/examples/thread_embedded_verilog_ipcore/thread_embedded_verilog_ipcore.py b/examples/thread_embedded_verilog_ipcore/thread_embedded_verilog_ipcore.py
@@ -219,4 +219,4 @@ def ctrl():
 """
 
     m = mkMemcpy()
-    ipcore.to_ipcore(m, 'myipcore', simcode=simcode, iftype='axi')
+    ipcore.to_ipcore(m, simcode=simcode, iftype='axi')
diff --git a/examples/thread_ipcore/Makefile b/examples/thread_ipcore/Makefile
@@ -13,7 +13,7 @@ all: test
 .PHONY: run
 run:
 	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
-	make compile run -C ipgen_*_v1_00_a/test/
+	make compile run -C *_v1_00_a/test/
 
 .PHONY: test
 test:
@@ -28,4 +28,4 @@ check:
 .PHONY: clean
 clean:
 	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd 
-	rm -rf ipgen_*_v1_00_a
+	rm -rf *_v1_00_a
diff --git a/examples/thread_ipcore/thread_ipcore.py b/examples/thread_ipcore/thread_ipcore.py
@@ -190,4 +190,4 @@ def ctrl():
 """
 
     m = mkLed()
-    ipcore.to_ipcore(m, 'myipcore', simcode=simcode, iftype='axi')
+    ipcore.to_ipcore(m, simcode=simcode, iftype='axi')
diff --git a/examples/thread_matmul_ipcore/Makefile b/examples/thread_matmul_ipcore/Makefile
@@ -13,7 +13,7 @@ all: test
 .PHONY: run
 run:
 	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
-	make compile run -C ipgen_*_v1_00_a/test/
+	make compile run -C *_v1_00_a/test/
 
 .PHONY: test
 test:
@@ -28,4 +28,4 @@ check:
 .PHONY: clean
 clean:
 	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd 
-	rm -rf ipgen_*_v1_00_a
+	rm -rf *_v1_00_a
diff --git a/examples/thread_matmul_ipcore/thread_matmul_ipcore.py b/examples/thread_matmul_ipcore/thread_matmul_ipcore.py
@@ -301,5 +301,4 @@ def ctrl():
 """
 
     m = mkLed()
-    ipcore.to_ipcore(m, 'myipcore', simcode=simcode,
-                     simmemimg=memname, iftype='axi')
+    ipcore.to_ipcore(m, simcode=simcode, simmemimg=memname, iftype='axi')
diff --git a/examples/thread_memcpy_ipcore/Makefile b/examples/thread_memcpy_ipcore/Makefile
@@ -13,7 +13,7 @@ all: test
 .PHONY: run
 run:
 	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
-	make compile run -C ipgen_*_v1_00_a/test/
+	make compile run -C *_v1_00_a/test/
 
 .PHONY: test
 test:
@@ -28,4 +28,4 @@ check:
 .PHONY: clean
 clean:
 	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd 
-	rm -rf ipgen_*_v1_00_a
+	rm -rf *_v1_00_a
diff --git a/examples/thread_memcpy_ipcore/thread_memcpy_ipcore.py b/examples/thread_memcpy_ipcore/thread_memcpy_ipcore.py
@@ -204,4 +204,4 @@ def ctrl():
 """
 
     m = mkMemcpy()
-    ipcore.to_ipcore(m, 'myipcore', simcode=simcode, iftype='axi')
+    ipcore.to_ipcore(m, simcode=simcode, iftype='axi')
diff --git a/examples/thread_verilog_submodule_ipcore/Makefile b/examples/thread_verilog_submodule_ipcore/Makefile
@@ -13,7 +13,7 @@ all: test
 .PHONY: run
 run:
 	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
-	make compile run -C ipgen_*_v1_00_a/test/
+	make compile run -C *_v1_00_a/test/
 
 .PHONY: test
 test:
@@ -28,4 +28,4 @@ check:
 .PHONY: clean
 clean:
 	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd 
-	rm -rf ipgen_*_v1_00_a
+	rm -rf *_v1_00_a
diff --git a/examples/thread_verilog_submodule_ipcore/thread_verilog_submodule_ipcore.py b/examples/thread_verilog_submodule_ipcore/thread_verilog_submodule_ipcore.py
@@ -314,4 +314,4 @@ def ctrl():
 """
 
     m = mkMemcpy()
-    ipcore.to_ipcore(m, 'myipcore', simcode=simcode, iftype='axi')
+    ipcore.to_ipcore(m, simcode=simcode, iftype='axi')
diff --git a/tests/extension/thread_/ipcore_axi_slave_lite/Makefile b/tests/extension/thread_/ipcore_axi_slave_lite/Makefile
@@ -13,7 +13,7 @@ all: test
 .PHONY: run
 run:
 	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
-	make compile run -C ipgen_*_v1_00_a/test/
+	make compile run -C *_v1_00_a/test/
 
 .PHONY: test
 test:
@@ -28,4 +28,4 @@ check:
 .PHONY: clean
 clean:
 	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd 
-	rm -rf ipgen_*_v1_00_a
+	rm -rf *_v1_00_a
diff --git a/tests/extension/thread_/ipcore_axi_slave_lite/thread_ipcore_axi_slave_lite.py b/tests/extension/thread_/ipcore_axi_slave_lite/thread_ipcore_axi_slave_lite.py
@@ -202,4 +202,4 @@ def ctrl():
 """
 
     m = mkLed()
-    ipcore.to_ipcore(m, 'myipcore', simcode=simcode, iftype='axi')
+    ipcore.to_ipcore(m, simcode=simcode, iftype='axi')
diff --git a/tests/extension/types_/ipcore_/master/Makefile b/tests/extension/types_/ipcore_/master/Makefile
@@ -27,4 +27,4 @@ check:
 .PHONY: clean
 clean:
 	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd 
-	rm -rf ipgen_*_v1_00_a
+	rm -rf *_v1_00_a
diff --git a/tests/extension/types_/ipcore_/slave_lite/Makefile b/tests/extension/types_/ipcore_/slave_lite/Makefile
@@ -27,4 +27,4 @@ check:
 .PHONY: clean
 clean:
 	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd 
-	rm -rf ipgen_*_v1_00_a
+	rm -rf *_v1_00_a
diff --git a/veriloggen/types/ipcore.py b/veriloggen/types/ipcore.py
@@ -11,19 +11,28 @@
 from . import axi
 
 
-def to_ipcore(m, name=None, clkname='CLK', rstname='RST',
+def to_ipcore(m, ipname=None, topname=None,
+              clkname='CLK', rstname='RST', iftype='axi',
               simaddrwidth=20, simcode=None, simmemimg=None,
-              iftype='axi', silent=False):
+              silent=False):
 
-    top = generate_top(m, name, clkname, rstname)
+    if topname is None:
+        topname = '_'.join(['top', m.name])
+
+    if ipname is None:
+        ipname = '_'.join([m.name, 'ip'])
+
+    top = generate_top(m, topname, clkname, rstname)
     verilog = top.to_verilog()
-    run_ipgen(top.name, verilog, simaddrwidth,
-              simcode, simmemimg, iftype, silent)
 
+    run_ipgen(topname, ipname, verilog,
+              iftype, simaddrwidth, simcode, simmemimg,
+              silent)
 
-def run_ipgen(topname, verilog,
-              simaddrwidth=20, simcode=None, simmemimg=None,
-              iftype='axi', silent=False):
+
+def run_ipgen(topname, ipname, verilog,
+              iftype='axi', simaddrwidth=20, simcode=None, simmemimg=None,
+              silent=False):
 
     # memory image
     if simmemimg is None:
@@ -74,11 +83,14 @@ def run_ipgen(topname, verilog,
     builder = ipgen.ipgen.SystemBuilder()
     builder.build(configs,
                   topmodule,
+                  ipname,
                   userlogic_filelist,
+
                   include=include,
                   define=define,
                   usertest=usertest,
                   memimg=memimg,
+
                   skip_not_found=skip_not_found,
                   ignore_protocol_error=ignore_protocol_error,
                   silent=silent)
@@ -92,13 +104,11 @@ def run_ipgen(topname, verilog,
         file_simcode.close()
 
 
-def generate_top(m, name=None, clkname='CLK', rstname='RST'):
+def generate_top(m, name, clkname='CLK', rstname='RST'):
+
     if not isinstance(m, module.Module):
         raise TypeError("'m' must be Module, not %s" % str(type(m)))
 
-    if name is None:
-        name = '_'.join(['top', m.name])
-
     masterbus = m.masterbus if hasattr(m, 'masterbus') else ()
     slavebus = m.slavebus if hasattr(m, 'slavebus') else ()
 
@@ -286,6 +296,7 @@ def mk_ipgen_slave_lite_memory():
 
     return m
 
+
 _master_memory = None
 _slave_memory = None
 _master_lite_memory = None
