modify bug in readRAM when latency = 2

Yasuhiro Nitta · Yasuhiro Nitta · commit dc84070c663b · 2020-04-30T17:56:20.000+09:00
diff --git a/veriloggen/stream/stypes.py b/veriloggen/stream/stypes.py
@@ -3505,6 +3505,7 @@ def _implement(self, m, seq, svalid=None, senable=None):
 
         if self.latency == 2:
             data = m.Wire(self.name('data'), datawidth, signed=signed)
+            data.assign(rdata)
             self.sig_data = data
 
         elif self.latency == 3:
