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1 parent 076a2c8 commit dc5e4c0Copy full SHA for dc5e4c0
veriloggen/types/util.py
@@ -54,9 +54,7 @@ def log2(value, maxsize=32):
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def add_mux(targ, cond, value):
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prev_assign = targ._get_assign()
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if not prev_assign:
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- # targ.assign(value)
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- # for easy debugging
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- targ.assign(vtypes.Mux(cond, value, value))
+ targ.assign(vtypes.Mux(cond, value, vtypes.IntX()))
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else:
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prev_value = prev_assign.statement.right
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prev_assign.overwrite_right(
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