correct parameter

shtaxxx · shtaxxx · commit da5e9f04f592 · 2017-10-07T23:49:28.000+09:00
diff --git a/veriloggen/types/axi.py b/veriloggen/types/axi.py
@@ -3085,7 +3085,7 @@ class AxiMemoryModel(object):
 
     def __init__(self, m, name, clk, rst,
                  datawidth=32, addrwidth=32,
-                 mem_datawidth=31, mem_addrwidth=20,
+                 mem_datawidth=32, mem_addrwidth=20,
                  memimg=None, write_delay=10, read_delay=10, sleep=4):
 
         if mem_datawidth % 8 != 0:
