Merge branch 'develop' into feature_axi_stream

Author: shtaxxx

veriloggen/stream/stypes.py

@@ -3505,6 +3505,7 @@ def _implement(self, m, seq, svalid=None, senable=None):
 
         if self.latency == 2:
             data = m.Wire(self.name('data'), datawidth, signed=signed)
+            data.assign(rdata)
             self.sig_data = data
 
         elif self.latency == 3: