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2 parents e9e7cc2 + c74ce6d commit d36bb8bCopy full SHA for d36bb8b
veriloggen/seq/reset_visitor.py
@@ -62,6 +62,8 @@ def visit_Cat(self, node):
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for v in node.vars:
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val = self.visit(v)
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width = v.bit_length()
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+ if width is None:
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+ width = 1
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if val is None:
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right = vtypes.IntX(width)
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elif isinstance(val.right, int):
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