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shtaxxxshtaxxx
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signed property of automatically added signals
1 parent da5e9f0 commit d159edf

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6 files changed

+64
-25
lines changed

6 files changed

+64
-25
lines changed

‎veriloggen/dataflow/dtypes.py‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -144,8 +144,8 @@ def output_tmp(self):
144144
raise ValueError("Module information is not set.")
145145

146146
tmp = self.m.get_tmp()
147-
self.output(self._tmp_data(tmp), self._tmp_valid(
148-
tmp), self._tmp_ready(tmp))
147+
self.output(self._tmp_data(tmp),
148+
self._tmp_valid(tmp), self._tmp_ready(tmp))
149149

150150
def prev(self, index):
151151
if index < 0:
@@ -2110,7 +2110,8 @@ def write(self, wdata, cond=None):
21102110
if hasattr(self, 'sig_data_write'):
21112111
data = self.sig_data_write
21122112
else:
2113-
data = self.m.TmpReg(self.bit_length(), initval=0)
2113+
data = self.m.TmpReg(self.bit_length(), initval=0,
2114+
signed=self.get_signed())
21142115
self.sig_data_write = data
21152116
self.sig_data.assign(data)
21162117
else:

‎veriloggen/fsm/fsm.py‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -505,6 +505,7 @@ def _add_delayed_subst(self, subst, index, delay):
505505
vtypes._Constant, vtypes._ParameterVariable)):
506506
return subst
507507
width = left.bit_length()
508+
signed = vtypes.get_signed(left)
508509
prev = right
509510

510511
name_prefix = ('_'.join(['', left.name, str(index), str(self.tmp_count)])
@@ -514,7 +515,7 @@ def _add_delayed_subst(self, subst, index, delay):
514515

515516
for i in range(delay):
516517
tmp_name = '_'.join([name_prefix, str(i + 1)])
517-
tmp = self.m.Reg(tmp_name, width, initval=0)
518+
tmp = self.m.Reg(tmp_name, width, initval=0, signed=signed)
518519
self._add_statement([tmp(prev)], delay=i, no_delay_cond=True)
519520
prev = tmp
520521
return left(prev)

‎veriloggen/seq/seq.py‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -127,10 +127,11 @@ def Prev(self, var, delay, initval=0, cond=None, prefix=None):
127127
prefix = '_'
128128

129129
width = var.bit_length()
130+
signed = vtypes.get_signed(var)
130131

131132
if not isinstance(var, vtypes._Variable):
132133
width = self.m.TmpLocalparam(width)
133-
w = self.m.TmpWire(width)
134+
w = self.m.TmpWire(width, signed=signed)
134135
w.assign(var)
135136
var = w
136137

@@ -143,7 +144,7 @@ def Prev(self, var, delay, initval=0, cond=None, prefix=None):
143144
for i in range(delay):
144145
cond = make_condition(cond)
145146
if cond is not None:
146-
tmp = self.m.TmpReg(width, initval=initval)
147+
tmp = self.m.TmpReg(var, width=width, initval=initval, signed=signed)
147148
self._add_statement([tmp(p)], cond=cond)
148149
p = tmp
149150

@@ -152,7 +153,7 @@ def Prev(self, var, delay, initval=0, cond=None, prefix=None):
152153
if tmp_name in self.prev_dict:
153154
p = self.prev_dict[tmp_name]
154155
continue
155-
tmp = self.m.Reg(tmp_name, width, initval=initval)
156+
tmp = self.m.Reg(tmp_name, width, initval=initval, signed=signed)
156157
self.prev_dict[tmp_name] = tmp
157158
self._add_statement([tmp(p)])
158159
p = tmp
@@ -458,6 +459,7 @@ def _add_delayed_subst(self, subst, delay):
458459
vtypes._Constant, vtypes._ParameterVariable)):
459460
return subst
460461
width = left.bit_length()
462+
signed = vtypes.get_signed(left)
461463
prev = right
462464

463465
name_prefix = ('_'.join(['', left.name, str(self.tmp_count)])
@@ -467,7 +469,7 @@ def _add_delayed_subst(self, subst, delay):
467469

468470
for i in range(delay):
469471
tmp_name = '_'.join([name_prefix, str(i + 1)])
470-
tmp = self.m.Reg(tmp_name, width, initval=0)
472+
tmp = self.m.Reg(tmp_name, width, initval=0, signed=signed)
471473
self._add_statement([tmp(prev)], delay=i, no_delay_cond=True)
472474
prev = tmp
473475
return left(prev)

‎veriloggen/thread/ttypes.py‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -653,7 +653,7 @@ def read_dataflow_interleave(self, port, addr, length=1,
653653
data_cond = dtypes.make_condition(data_ack, last_ack)
654654
prev_data_cond = self.seq.Prev(data_cond, 1)
655655

656-
data_list = [self.m.TmpWireLike(ram.interfaces[port].rdata)
656+
data_list = [self.m.TmpWireLike(ram.interfaces[port].rdata, signed=True)
657657
for ram in self.rams]
658658

659659
prev_data_list = [self.seq.Prev(data, 1) for data in data_list]
@@ -683,7 +683,7 @@ def read_dataflow_interleave(self, port, addr, length=1,
683683
prev_patterns = [(prev_reg_bank_sel == i, data)
684684
for i, data in enumerate(prev_data_list)]
685685
prev_patterns.append((None, 0))
686-
data = self.m.TmpWire(self.orig_datawidth)
686+
data = self.m.TmpWire(self.orig_datawidth, signed=True)
687687
data.assign(vtypes.Mux(prev_data_cond,
688688
vtypes.PatternMux(*patterns),
689689
vtypes.PatternMux(*prev_patterns)))
@@ -784,7 +784,7 @@ def read_dataflow_pattern_interleave(self, port, addr, pattern,
784784
data_cond = dtypes.make_condition(data_ack, last_ack)
785785
prev_data_cond = self.seq.Prev(data_cond, 1)
786786

787-
data_list = [self.m.TmpWireLike(ram.interfaces[port].rdata)
787+
data_list = [self.m.TmpWireLike(ram.interfaces[port].rdata, signed=True)
788788
for ram in self.rams]
789789

790790
prev_data_list = [self.seq.Prev(data, 1) for data in data_list]
@@ -809,7 +809,7 @@ def read_dataflow_pattern_interleave(self, port, addr, pattern,
809809
prev_patterns = [(prev_reg_bank_sel == i, data)
810810
for i, data in enumerate(prev_data_list)]
811811
prev_patterns.append((None, 0))
812-
data = self.m.TmpWire(self.orig_datawidth)
812+
data = self.m.TmpWire(self.orig_datawidth, signed=True)
813813
data.assign(vtypes.Mux(prev_data_cond,
814814
vtypes.PatternMux(*patterns),
815815
vtypes.PatternMux(*prev_patterns)))
@@ -1361,7 +1361,7 @@ def read(self, fsm, global_addr):
13611361
else:
13621362
data, valid = ret
13631363

1364-
rdata = self.m.TmpReg(self.datawidth, initval=0)
1364+
rdata = self.m.TmpReg(self.datawidth, initval=0, signed=True)
13651365
fsm.If(valid)(rdata(data))
13661366
fsm.Then().goto_next()
13671367

@@ -1803,12 +1803,12 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
18031803
str(type(length)))
18041804

18051805
self.register = [self.m.Reg('_'.join(['', self.name, 'register', '%d' % i]),
1806-
width=self.datawidth, initval=0)
1806+
width=self.datawidth, initval=0, signed=True)
18071807
for i in range(length)]
18081808
self.flag = [self.m.Reg('_'.join(['', self.name, 'flag', '%d' % i]), initval=0)
18091809
for i in range(length)]
18101810
self.resetval = [self.m.Reg('_'.join(['', self.name, 'resetval', '%d' % i]),
1811-
width=self.datawidth, initval=0)
1811+
width=self.datawidth, initval=0, signed=True)
18121812
for i in range(length)]
18131813
self.length = length
18141814
self.maskwidth = self.m.Localparam('_'.join(['', self.name, 'maskwidth']),
@@ -1842,7 +1842,7 @@ def _setup_register_lite_fsm(self):
18421842
fsm.If(readvalid).goto_from(init_state, read_state)
18431843
fsm.set_index(read_state)
18441844

1845-
rdata = self.m.TmpWire(self.datawidth)
1845+
rdata = self.m.TmpWire(self.datawidth, signed=True)
18461846
pat = [(maskaddr == i, r) for i, r in enumerate(self.register)]
18471847
pat.append((None, vtypes.IntX()))
18481848
rval = vtypes.PatternMux(pat)
@@ -1854,7 +1854,7 @@ def _setup_register_lite_fsm(self):
18541854
rval = vtypes.PatternMux(pat)
18551855
flag.assign(rval)
18561856

1857-
resetval = self.m.TmpWire(self.datawidth)
1857+
resetval = self.m.TmpWire(self.datawidth, signed=True)
18581858
pat = [(maskaddr == i, r) for i, r in enumerate(self.resetval)]
18591859
pat.append((None, vtypes.IntX()))
18601860
rval = vtypes.PatternMux(pat)
@@ -1905,7 +1905,7 @@ def _setup_register_full_fsm(self):
19051905
fsm.If(readvalid).goto_from(init_state, read_state)
19061906
fsm.set_index(read_state)
19071907

1908-
rdata = self.m.TmpWire(self.datawidth)
1908+
rdata = self.m.TmpWire(self.datawidth, signed=True)
19091909
pat = [(maskaddr == i, r) for i, r in enumerate(self.register)]
19101910
pat.append((None, vtypes.IntX()))
19111911
rval = vtypes.PatternMux(pat)
@@ -1917,7 +1917,7 @@ def _setup_register_full_fsm(self):
19171917
rval = vtypes.PatternMux(pat)
19181918
flag.assign(rval)
19191919

1920-
resetval = self.m.TmpWire(self.datawidth)
1920+
resetval = self.m.TmpWire(self.datawidth, signed=True)
19211921
pat = [(maskaddr == i, r) for i, r in enumerate(self.resetval)]
19221922
pat.append((None, vtypes.IntX()))
19231923
rval = vtypes.PatternMux(pat)

‎veriloggen/types/axi.py‎

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3081,6 +3081,8 @@ def AxiLiteSlave(m, name, clk, rst, datawidth=32, addrwidth=32,
30813081

30823082

30833083
class AxiMemoryModel(object):
3084+
__intrinsics__ = ('read', 'write')
3085+
30843086
burst_size_width = 8
30853087

30863088
def __init__(self, m, name, clk, rst,
@@ -3335,3 +3337,36 @@ def connect(self, ports, name):
33353337
rlast.connect(self.rdata.rlast)
33363338
rvalid.connect(self.rdata.rvalid)
33373339
self.rdata.rready.connect(rready)
3340+
3341+
def read(self, fsm, addr):
3342+
""" intrinsic for thread """
3343+
3344+
cond = fsm.state == fsm.current
3345+
rdata = self.m.TmpReg(self.mem_datawidth, initval=0, signed=True)
3346+
num_bytes = self.mem_datawidth // 8
3347+
3348+
fsm.If(cond)(
3349+
rdata(vtypes.Cat(*reversed([self.mem[addr + i]
3350+
for i in range(num_bytes)])))
3351+
)
3352+
fsm.goto_next()
3353+
3354+
return rdata
3355+
3356+
def write(self, fsm, addr, wdata):
3357+
""" intrinsic for thread """
3358+
3359+
cond = fsm.state == fsm.current
3360+
num_bytes = self.mem_datawidth // 8
3361+
3362+
wdata_wire = self.m.TmpWire(self.mem_datawidth)
3363+
wdata_wire.assign(wdata)
3364+
3365+
for i in range(num_bytes):
3366+
self.fsm.seq.If(cond)(
3367+
self.mem[addr + i](wdata_wire[i * 8:i * 8 + 8])
3368+
)
3369+
3370+
fsm.goto_next()
3371+
3372+
return 0

‎veriloggen/types/ram.py‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -273,7 +273,7 @@ def read_dataflow(self, port, addr, length=1,
273273
data_cond = make_condition(data_ack, last_ack)
274274
prev_data_cond = self.seq.Prev(data_cond, 1)
275275

276-
data = self.m.TmpWireLike(self.interfaces[port].rdata)
276+
data = self.m.TmpWireLike(self.interfaces[port].rdata, signed=True)
277277

278278
prev_data = self.seq.Prev(data, 1)
279279
data.assign(vtypes.Mux(prev_data_cond,
@@ -361,7 +361,7 @@ def read_dataflow_pattern(self, port, addr, pattern,
361361
data_cond = make_condition(data_ack, last_ack)
362362
prev_data_cond = self.seq.Prev(data_cond, 1)
363363

364-
data = self.m.TmpWireLike(self.interfaces[port].rdata)
364+
data = self.m.TmpWireLike(self.interfaces[port].rdata, signed=True)
365365

366366
prev_data = self.seq.Prev(data, 1)
367367
data.assign(vtypes.Mux(prev_data_cond,
@@ -540,9 +540,9 @@ def read_dataflow_reuse(self, port, addr, length=1,
540540
counter = self.m.TmpReg(length.bit_length() + 1, initval=0)
541541

542542
last = self.m.TmpReg(initval=0)
543-
reuse_data = [self.m.TmpReg(self.datawidth, initval=0)
543+
reuse_data = [self.m.TmpReg(self.datawidth, initval=0, signed=True)
544544
for _ in range(num_outputs)]
545-
next_reuse_data = [self.m.TmpReg(self.datawidth, initval=0)
545+
next_reuse_data = [self.m.TmpReg(self.datawidth, initval=0, signed=True)
546546
for _ in range(num_outputs)]
547547

548548
reuse_count = self.m.TmpReg(reuse_size.bit_length() + 1, initval=0)
@@ -710,9 +710,9 @@ def read_dataflow_reuse_pattern(self, port, addr, pattern,
710710
for (out_size, out_stride) in pattern]
711711

712712
last = self.m.TmpReg(initval=0)
713-
reuse_data = [self.m.TmpReg(self.datawidth, initval=0)
713+
reuse_data = [self.m.TmpReg(self.datawidth, initval=0, signed=True)
714714
for _ in range(num_outputs)]
715-
next_reuse_data = [self.m.TmpReg(self.datawidth, initval=0)
715+
next_reuse_data = [self.m.TmpReg(self.datawidth, initval=0, singed=True)
716716
for _ in range(num_outputs)]
717717

718718
reuse_count = self.m.TmpReg(reuse_size.bit_length() + 1, initval=0)

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