thread_stream_matmul

Author: shtaxxx

examples/thread_matmul/test_thread_matmul.py

@@ -12,11 +12,17 @@
 import veriloggen.types.axi as axi
 
 
-def mkLed():
+def mkLed(matrix_size=16):
     m = Module('blinkled')
     clk = m.Input('CLK')
     rst = m.Input('RST')
 
+    seq = Seq(m, 'seq', clk, rst)
+    timer = m.Reg('timer', 32, initval=0)
+    seq(
+        timer.inc()
+    )
+
     datawidth = 32
     addrwidth = 10
     ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
@@ -25,7 +31,11 @@ def mkLed():
     myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
 
     def matmul(matrix_size, a_offset, b_offset, c_offset):
+        start_time = timer
         comp(matrix_size, a_offset, b_offset, c_offset)
+        end_time = timer
+        time = end_time - start_time
+        print("Time (cycles): %d" % time)
         check(matrix_size, a_offset, b_offset, c_offset)
 
     def comp(matrix_size, a_offset, b_offset, c_offset):
@@ -60,8 +70,10 @@ def check(matrix_size, a_offset, b_offset, c_offset):
                 v = ram_c.read(j)
                 if i == j and v != (i + 1) * 2:
                     all_ok = False
+                    print("NG [%d,%d] = %d" % (i, j, v))
                 if i != j and v != 0:
                     all_ok = False
+                    print("NG [%d,%d] = %d" % (i, j, v))
             c_addr += matrix_size * (datawidth // 8)
 
         if all_ok:
@@ -70,16 +82,18 @@ def check(matrix_size, a_offset, b_offset, c_offset):
             print("NG")
 
     th = vthread.Thread(m, 'th_matmul', clk, rst, matmul)
-    fsm = th.start(16, 0, 1024, 2048)
+    fsm = th.start(matrix_size, 0, 1024, 2048)
 
     return m
 
 
 def mkTest():
     m = Module('test')
 
+    matrix_size = 16
+
     # target instance
-    led = mkLed()
+    led = mkLed(matrix_size)
 
     # copy paras and ports
     params = m.copy_params(led)
@@ -102,8 +116,8 @@ def fwrite(f, value):
         # ram_a
         addr = 0
         nv = 1
-        for x in range(16):
-            for y in range(16):
+        for x in range(matrix_size):
+            for y in range(matrix_size):
                 addr += 4
                 if x == y:
                     value = nv
@@ -117,8 +131,8 @@ def fwrite(f, value):
 
         # ram_b
         addr = 1024
-        for x in range(16):
-            for y in range(16):
+        for x in range(matrix_size):
+            for y in range(matrix_size):
                 addr += 4
                 if x == y:
                     value = 2
@@ -131,8 +145,8 @@ def fwrite(f, value):
 
         # ram_c
         addr = 2048
-        for x in range(16):
-            for y in range(16):
+        for x in range(matrix_size):
+            for y in range(matrix_size):
                 addr += 4
                 value = 100
                 fwrite(f, value)

examples/thread_matmul/thread_matmul.py

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd