read_verilog_ test is updated. read_verilog_pycoram_object does not work correctly. read_verilog method should be modified to support the include path option.

shtaxxx · shtaxxx · commit cd7bb0e40eef · 2015-10-30T12:50:20.000+09:00
diff --git a/tests/read_verilog_/module/read_verilog_module.py b/tests/read_verilog_/module/read_verilog_module.py
@@ -2,10 +2,14 @@
 import os
 import collections
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
-    modules = read_verilog_module('led.v')
+    filename = os.path.dirname(os.path.abspath(__file__)) + '/led.v'
+    modules = read_verilog_module(filename)
     m = modules['blinkled']
     return m
 
diff --git a/tests/read_verilog_/module/test_read_verilog_module.py b/tests/read_verilog_/module/test_read_verilog_module.py
@@ -1,4 +1,4 @@
-import led
+import read_verilog_module
 
 expected_verilog = """
 module top #
@@ -55,9 +55,9 @@
 endmodule
 """
 
-def test_led():
-    top_module = led.mkTop()
-    top_code = top_module.to_verilog()
+def test():
+    test_module = read_verilog_module.mkTop()
+    code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
@@ -66,4 +66,4 @@ def test_led():
     codegen = ASTCodeGenerator()
     expected_code = codegen.visit(expected_ast)
 
-    assert(expected_code == top_code)
+    assert(expected_code == code)
diff --git a/tests/read_verilog_/module_generate/read_verilog_module_generate.py b/tests/read_verilog_/module_generate/read_verilog_module_generate.py
@@ -2,10 +2,14 @@
 import os
 import collections
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
-    modules = read_verilog_module('led.v')
+    filename = os.path.dirname(os.path.abspath(__file__)) + '/led.v'
+    modules = read_verilog_module(filename)
     m = modules['blinkled']
     return m
 
diff --git a/tests/read_verilog_/module_generate/test_read_verilog_module_generate.py b/tests/read_verilog_/module_generate/test_read_verilog_module_generate.py
@@ -1,4 +1,4 @@
-import led
+import read_verilog_module_generate
 
 expected_verilog = """
 module top #
@@ -75,9 +75,9 @@
 endmodule
 """
 
-def test_led():
-    top_module = led.mkTop()
-    top_code = top_module.to_verilog()
+def test():
+    test_module = read_verilog_module_generate.mkTop()
+    code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
@@ -86,4 +86,4 @@ def test_led():
     codegen = ASTCodeGenerator()
     expected_code = codegen.visit(expected_ast)
 
-    assert(expected_code == top_code)
+    assert(expected_code == code)
diff --git a/tests/read_verilog_/module_initial/read_verilog_module_initial.py b/tests/read_verilog_/module_initial/read_verilog_module_initial.py
@@ -2,10 +2,14 @@
 import os
 import collections
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLedTest():
-    modules = read_verilog_module('led.v')
+    filename = os.path.dirname(os.path.abspath(__file__)) + '/led.v'
+    modules = read_verilog_module(filename)
     led = modules['blinkled']
     test = modules['test']
     return led, test
diff --git a/tests/read_verilog_/module_initial/test_read_verilog_module_initial.py b/tests/read_verilog_/module_initial/test_read_verilog_module_initial.py
@@ -1,4 +1,4 @@
-import led
+import read_verilog_module_initial
 
 expected_verilog = """
 module test #
@@ -76,10 +76,9 @@
 endmodule
 """
 
-def test_led():
-    led_module, test = led.mkLedTest()
-    code = ''.join([ test.to_verilog(), led_module.to_verilog() ])
-
+def test():
+    test_module, test_bench = read_verilog_module_initial.mkLedTest()
+    code = ''.join([ test_bench.to_verilog(), test_module.to_verilog() ])
     from pyverilog.vparser.parser import VerilogParser
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
     parser = VerilogParser()
diff --git a/tests/read_verilog_/module_modify/read_verilog_module_modify.py b/tests/read_verilog_/module_modify/read_verilog_module_modify.py
@@ -2,10 +2,14 @@
 import os
 import collections
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
-    modules = read_verilog_module('led.v')
+    filename = os.path.dirname(os.path.abspath(__file__)) + '/led.v'
+    modules = read_verilog_module(filename)
     m = modules['blinkled']
     
     # change the module name
diff --git a/tests/read_verilog_/module_modify/test_read_verilog_module_modify.py b/tests/read_verilog_/module_modify/test_read_verilog_module_modify.py
@@ -1,4 +1,4 @@
-import led
+import read_verilog_module_modify
 
 expected_verilog = """
 module top #
@@ -58,9 +58,9 @@
 endmodule
 """
 
-def test_led():
-    top_module = led.mkTop()
-    top_code = top_module.to_verilog()
+def test():
+    test_module = read_verilog_module_modify.mkTop()
+    code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
@@ -69,4 +69,4 @@ def test_led():
     codegen = ASTCodeGenerator()
     expected_code = codegen.visit(expected_ast)
 
-    assert(expected_code == top_code)
+    assert(expected_code == code)
diff --git a/tests/read_verilog_/module_str/read_verilog_module_str.py b/tests/read_verilog_/module_str/read_verilog_module_str.py
@@ -2,6 +2,9 @@
 import os
 import collections
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 led_v = '''
diff --git a/tests/read_verilog_/module_str/test_read_verilog_module_str.py b/tests/read_verilog_/module_str/test_read_verilog_module_str.py
@@ -1,4 +1,4 @@
-import led
+import read_verilog_module_str
 
 expected_verilog = """
 module top #
@@ -55,9 +55,9 @@
 endmodule
 """
 
-def test_led():
-    top_module = led.mkTop()
-    top_code = top_module.to_verilog()
+def test():
+    test_module = read_verilog_module_str.mkTop()
+    code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
@@ -66,4 +66,4 @@ def test_led():
     codegen = ASTCodeGenerator()
     expected_code = codegen.visit(expected_ast)
 
-    assert(expected_code == top_code)
+    assert(expected_code == code)
diff --git a/tests/read_verilog_/pycoram_ctrl_thread/read_verilog_pycoram_ctrl_thread.py b/tests/read_verilog_/pycoram_ctrl_thread/read_verilog_pycoram_ctrl_thread.py
@@ -2,10 +2,14 @@
 import os
 import collections
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkThread():
-    modules = read_verilog_module('ctrl_thread.v')
+    filename = os.path.dirname(os.path.abspath(__file__)) + '/ctrl_thread.v'
+    modules = read_verilog_module(filename)
     return modules
 
 if __name__ == '__main__':
diff --git a/tests/read_verilog_/pycoram_ctrl_thread/test_read_verilog_pycoram_ctrl_thread.py b/tests/read_verilog_/pycoram_ctrl_thread/test_read_verilog_pycoram_ctrl_thread.py
@@ -1,4 +1,4 @@
-import led
+import read_verilog_pycoram_ctrl_thread
 
 expected_verilog = """
 module ctrl_thread
@@ -241,8 +241,8 @@
 endmodule
 """
 
-def test_led():
-    modules = led.mkThread()
+def test():
+    modules = read_verilog_pycoram_ctrl_thread.mkThread()
     code = ''.join([ m.to_verilog() for m in modules.values() ])
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/read_verilog_/pycoram_object/read_verilog_pycoram_object.py b/tests/read_verilog_/pycoram_object/read_verilog_pycoram_object.py
@@ -2,10 +2,14 @@
 import os
 import collections
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkUserlogic():
-    modules = read_verilog_module('userlogic.v')
+    filename = os.path.dirname(os.path.abspath(__file__)) + '/userlogic.v'
+    modules = read_verilog_module(filename)
     return modules
 
 if __name__ == '__main__':
diff --git a/tests/read_verilog_/pycoram_object/test_read_verilog_pycoram_object.py b/tests/read_verilog_/pycoram_object/test_read_verilog_pycoram_object.py
@@ -1,4 +1,4 @@
-import led
+import read_verilog_pycoram_object
 
 expected_verilog = """
 module CoramMemory1P #
@@ -293,8 +293,8 @@
 endmodule
 """
 
-def test_led():
-    modules = led.mkUserlogic()
+def test():
+    modules = read_verilog_pycoram_object.mkUserlogic()
     code = ''.join([ m.to_verilog() for m in modules.values() ])
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/read_verilog_/stub_module/read_verilog_stub_module.py b/tests/read_verilog_/stub_module/read_verilog_stub_module.py
@@ -2,10 +2,14 @@
 import os
 import collections
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 def mkLed():
-    stubs = read_verilog_stubmodule('led.v')
+    filename = os.path.dirname(os.path.abspath(__file__)) + '/led.v'
+    stubs = read_verilog_stubmodule(filename)
     m = stubs['blinkled']
     return m
 
diff --git a/tests/read_verilog_/stub_module/test_read_verilog_stub_module.py b/tests/read_verilog_/stub_module/test_read_verilog_stub_module.py
@@ -1,4 +1,4 @@
-import led
+import read_verilog_stub_module
 
 expected_verilog = """
 module top #
@@ -23,9 +23,9 @@
 endmodule
 """
 
-def test_led():
-    top_module = led.mkTop()
-    top_code = top_module.to_verilog()
+def test():
+    test_module = read_verilog_stub_module.mkTop()
+    code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
@@ -34,4 +34,4 @@ def test_led():
     codegen = ASTCodeGenerator()
     expected_code = codegen.visit(expected_ast)
 
-    assert(expected_code == top_code)
+    assert(expected_code == code)
diff --git a/tests/read_verilog_/stub_module_str/read_verilog_stub_module_str.py b/tests/read_verilog_/stub_module_str/read_verilog_stub_module_str.py
@@ -2,6 +2,9 @@
 import os
 import collections
 
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
+
 from veriloggen import *
 
 led_v = '''
diff --git a/tests/read_verilog_/stub_module_str/test_read_verilog_stub_module_str.py b/tests/read_verilog_/stub_module_str/test_read_verilog_stub_module_str.py
@@ -1,4 +1,4 @@
-import led
+import read_verilog_stub_module_str
 
 expected_verilog = """
 module top #
@@ -23,9 +23,9 @@
 endmodule
 """
 
-def test_led():
-    top_module = led.mkTop()
-    top_code = top_module.to_verilog()
+def test():
+    test_module = read_verilog_stub_module_str.mkTop()
+    code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
@@ -34,4 +34,4 @@ def test_led():
     codegen = ASTCodeGenerator()
     expected_code = codegen.visit(expected_ast)
 
-    assert(expected_code == top_code)
+    assert(expected_code == code)
