stream.Reg

Author: shtaxxx

tests/extension/thread_/stream_reg/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

tests/extension/thread_/stream_reg/test_thread_stream_reg.py

@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_stream_reg
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_stream_reg.run(filename=None, simtype=simtype,
+                                 outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')

tests/extension/thread_/stream_reg/thread_stream_reg.py

@@ -0,0 +1,145 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    datawidth = 32
+    addrwidth = 10
+    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
+    ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
+    ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
+
+    strm = vthread.Stream(m, 'mystream', clk, rst)
+
+    a = strm.source('a')
+
+    # to extern
+
+    when = a < 4
+    r = strm.Reg(a, when)
+
+    # from extern
+    b = r + 100
+
+    strm.sink(b, 'b')
+
+    def comp_stream(size, offset):
+        strm.set_source('a', ram_a, offset, size)
+        strm.set_sink('b', ram_b, offset, size)
+        strm.run()
+        strm.join()
+
+    def comp_sequential(size, offset):
+        r = 0
+        for i in range(size):
+            a = ram_a.read(i + offset)
+            if a < 4:
+                r = a
+            b = r + 100
+            ram_b.write(i + offset, b)
+
+    def check(size, offset_stream, offset_seq):
+        all_ok = True
+        for i in range(size):
+            st = ram_b.read(i + offset_stream)
+            sq = ram_b.read(i + offset_seq)
+            if vthread.verilog.NotEql(st, sq):
+                all_ok = False
+        if all_ok:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+    def comp(size):
+        # stream
+        offset = 0
+        myaxi.dma_read(ram_a, offset, 0, size)
+        comp_stream(size, offset)
+        myaxi.dma_write(ram_b, offset, 1024, size)
+
+        # sequential
+        offset = size * 4
+        myaxi.dma_read(ram_a, offset, 0, size)
+        comp_sequential(size, offset)
+        myaxi.dma_write(ram_b, offset, 1024 * 2, size)
+
+        # verification
+        check(size, 0, offset)
+
+        vthread.finish()
+
+    th = vthread.Thread(m, 'th_comp', clk, rst, comp)
+    fsm = th.start(32)
+
+    return m
+
+
+def mkTest(memimg_name=None):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
+    memory.connect(ports, 'myaxi')
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    #simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    sim = simulation.Simulator(test, sim=simtype)
+    rslt = sim.run(outputfile=outputfile)
+    lines = rslt.splitlines()
+    if simtype == 'verilator' and lines[-1].startswith('-'):
+        rslt = '\n'.join(lines[:-1])
+    return rslt
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)

veriloggen/stream/stypes.py

@@ -3171,6 +3171,43 @@ def _implement(self, m, seq, svalid=None, senable=None):
         self.sig_data = data
 
 
+class Reg(_SpecialOperator):
+    latency = 1
+
+    def __init__(self, data, when=None):
+
+        args = [data]
+        if when is not None:
+            args.append(when)
+
+        _SpecialOperator.__init__(self, *args)
+
+        self.width = data.bit_length()
+        self.point = data.get_point()
+        self.signed = data.get_signed()
+
+        self.graph_label = 'Reg'
+        self.graph_shape = 'box'
+
+    def _implement(self, m, seq, svalid=None, senable=None):
+        if self.latency != 1:
+            raise ValueError("Latency mismatch '%d' != '%s'" %
+                             (self.latency, 1))
+
+        width = self.bit_length()
+        signed = self.get_signed()
+
+        arg_data = [arg.sig_data for arg in self.args]
+
+        data = m.Reg(self.name('data'), width, initval=0, signed=signed)
+        self.sig_data = data
+
+        when_cond = self.args[1].sig_data if len(self.args) == 2 else None
+        enable = _and_vars(senable, when_cond)
+
+        seq(data(arg_data[0]), cond=enable)
+
+
 class ReadRAM(_SpecialOperator):
     latency = 3