rename from strm.Xorshift to strm.RandXorshift

Author: sh-mug

tests/extension/thread_/stream_xorshift/Makefile renamed to tests/extension/thread_/stream_rand_xorshift/Makefile

@@ -3,15 +3,15 @@
 
 import os
 import veriloggen
-import thread_stream_xorshift
+import thread_stream_rand_xorshift
 
 
 def test(request):
     veriloggen.reset()
 
     simtype = request.config.getoption('--sim')
 
-    rslt = thread_stream_xorshift.run(filename=None, simtype=simtype,
+    rslt = thread_stream_rand_xorshift.run(filename=None, simtype=simtype,
                                      outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
 
     verify_rslt = rslt.splitlines()[-1]

tests/extension/thread_/stream_xorshift/test_thread_stream_xorshift.py renamed to tests/extension/thread_/stream_rand_xorshift/test_thread_stream_rand_xorshift.py

@@ -26,7 +26,7 @@ def mkLed():
     ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
 
     strm = vthread.Stream(m, 'mystream', clk, rst)
-    rand_hard = strm.Xorshift(initval=initval)
+    rand_hard = strm.RandXorshift(initval=initval)
     a = strm.source('a')
     b = strm.source('b')
     c = a + b - a - b + rand_hard

tests/extension/thread_/stream_xorshift/thread_stream_xorshift.py renamed to tests/extension/thread_/stream_rand_xorshift/thread_stream_rand_xorshift.py

@@ -3630,7 +3630,7 @@ def _implement(self, m, seq, svalid=None, senable=None):
         seq(count(next_count_value), cond=enable_cond)
 
 
-class Xorshift(_Accumulator):
+class RandXorshift(_Accumulator):
 
     def __init__(self, initval=0x12345678, dependency=None, enable=None, reset=None,
                  reg_initval=None, width=32):
@@ -3642,7 +3642,7 @@ def __init__(self, initval=0x12345678, dependency=None, enable=None, reset=None,
 
         _Accumulator.__init__(self, right, size, interval, initval, offset,
                               dependency, enable, reset, reg_initval, width, signed)
-        self.graph_label = 'XorShift'
+        self.graph_label = 'RandXorshift'
 
     def _implement(self, m, seq, svalid=None, senable=None):
         if self.latency != 1: