File tree Expand file tree Collapse file tree 2 files changed +8
-5
lines changed Expand file tree Collapse file tree 2 files changed +8
-5
lines changed Original file line number Diff line number Diff line change 7979Getting Started
8080==============================
8181
82- You can find some examples in 'veriloggen/sample/'.
82+ You can find some examples in 'veriloggen/sample/' and 'veriloggen/tests' .
8383
8484Let's begin veriloggen by an example. Create a example Python script in Python as below. A blinking LED hardware is modeled in Python.
85+ Open 'led.py' in the root directory.
8586
8687``` python
8788import sys
@@ -131,7 +132,7 @@ Run the script.
131132python led.py
132133```
133134
134- You will have a complete Verilog HDL source code that is generated by the source code generator of Pyverilog .
135+ You will have a complete Verilog HDL source code that is generated by the source code generator.
135136
136137``` verilog
137138module blinkled #
Original file line number Diff line number Diff line change @@ -89,10 +89,12 @@ without any installation on your host platform.
8989Getting Started
9090===============
9191
92- You can find some examples in 'veriloggen/sample/'.
92+ You can find some examples in 'veriloggen/sample/' and
93+ 'veriloggen/tests'.
9394
9495Let's begin veriloggen by an example. Create a example Python script in
95- Python as below. A blinking LED hardware is modeled in Python.
96+ Python as below. A blinking LED hardware is modeled in Python. Open
97+ 'led.py' in the root directory.
9698
9799.. code :: python
98100
@@ -143,7 +145,7 @@ Run the script.
143145 python led.py
144146
145147You will have a complete Verilog HDL source code that is generated by
146- the source code generator of Pyverilog .
148+ the source code generator.
147149
148150.. code :: verilog
149151
You can’t perform that action at this time.
0 commit comments