Method names are changed: Module.reset() -> Module.make_reset(), FSM.to_case -> FSM.make_case()

Author: shtaxxx

sample/bram/bram.py

@@ -101,7 +101,7 @@ def mkTop():
             bramif.addr(0), bramif.datain(0), bramif.write(0), fsm.set_init()
         ).Else(
             # inserting FSM body
-            *fsm.to_if()
+            fsm.make_if()
         ))
 
     return m

sample/fsm/led.py

@@ -45,10 +45,10 @@ def mkLed():
     # build always statement
     m.Always(Posedge(clk))(
         If(rst)(
-            m.reset(),
+            m.make_reset(),
         ).Else(
             count(count + 1),
-            fsm.to_case()
+            fsm.make_case()
         ))
 
     return m
@@ -66,7 +66,7 @@ def mkTest():
 
     lib.simulation.setup_waveform(m, uut)
     lib.simulation.setup_clock(m, clk, hperiod=5)
-    init = lib.simulation.setup_reset(m, rst, m.reset(), period=100)
+    init = lib.simulation.setup_reset(m, rst, m.make_reset(), period=100)
 
     init.add(
         [ lib.simulation.next_clock(clk) for i in range(8) ],

sample/fsm/test_led.py

@@ -36,13 +36,21 @@
     #100;
     RST = 0;
     @(posedge CLK);
+    #1;
     @(posedge CLK);
+    #1;
     @(posedge CLK);
+    #1;
     @(posedge CLK);
+    #1;
     @(posedge CLK);
+    #1;
     @(posedge CLK);
+    #1;
     @(posedge CLK);
+    #1;
     @(posedge CLK);
+    #1;
     ready = 1;
     #1000;
     $finish;
@@ -64,166 +72,166 @@
   localparam fsm_init = 0;
   localparam fsm_1 = 1;
   localparam fsm_2 = 2;
-  reg [(32 - 1):0] d1_fsm;
+  reg [(32 - 1):0] _d1_fsm;
   localparam fsm_3 = 3;
   localparam fsm_4 = 4;
-  reg fsm_cond_4_1_0;
+  reg _fsm_cond_4_1_0;
   localparam fsm_5 = 5;
   localparam fsm_6 = 6;
   localparam fsm_7 = 7;
-  reg fsm_cond_7_1_1;
-  reg [(32 - 1):0] d2_fsm;
-  reg fsm_cond_7_2_2;
-  reg fsm_cond_7_2_3;
-  reg [(32 - 1):0] d3_fsm;
-  reg fsm_cond_7_3_4;
-  reg fsm_cond_7_3_5;
-  reg fsm_cond_7_3_6;
+  reg _fsm_cond_7_1_1;
+  reg [(32 - 1):0] _d2_fsm;
+  reg _fsm_cond_7_2_2;
+  reg _fsm_cond_7_2_3;
+  reg [(32 - 1):0] _d3_fsm;
+  reg _fsm_cond_7_3_4;
+  reg _fsm_cond_7_3_5;
+  reg _fsm_cond_7_3_6;
   localparam fsm_8 = 8;
-  reg fsm_cond_8_1_7;
-  reg fsm_cond_8_2_8;
-  reg fsm_cond_8_2_9;
-  reg fsm_cond_8_3_10;
-  reg fsm_cond_8_3_11;
-  reg fsm_cond_8_3_12;
+  reg _fsm_cond_8_1_7;
+  reg _fsm_cond_8_2_8;
+  reg _fsm_cond_8_2_9;
+  reg _fsm_cond_8_3_10;
+  reg _fsm_cond_8_3_11;
+  reg _fsm_cond_8_3_12;
   localparam fsm_9 = 9;
-  reg fsm_cond_9_1_13;
-  reg fsm_cond_9_2_14;
-  reg fsm_cond_9_2_15;
-  reg fsm_cond_9_3_16;
-  reg fsm_cond_9_3_17;
-  reg fsm_cond_9_3_18;
+  reg _fsm_cond_9_1_13;
+  reg _fsm_cond_9_2_14;
+  reg _fsm_cond_9_2_15;
+  reg _fsm_cond_9_3_16;
+  reg _fsm_cond_9_3_17;
+  reg _fsm_cond_9_3_18;
   localparam fsm_10 = 10;
-  reg fsm_cond_10_1_19;
-  reg fsm_cond_10_2_20;
-  reg fsm_cond_10_2_21;
-  reg fsm_cond_10_3_22;
-  reg fsm_cond_10_3_23;
-  reg fsm_cond_10_3_24;
+  reg _fsm_cond_10_1_19;
+  reg _fsm_cond_10_2_20;
+  reg _fsm_cond_10_2_21;
+  reg _fsm_cond_10_3_22;
+  reg _fsm_cond_10_3_23;
+  reg _fsm_cond_10_3_24;
   localparam fsm_11 = 11;
 
   always @(posedge CLK) begin
     if(RST) begin
       valid <= 0;
       count <= 0;
       fsm <= fsm_init;
-      d1_fsm <= fsm_init;
-      fsm_cond_4_1_0 <= 0;
-      fsm_cond_7_1_1 <= 0;
-      d2_fsm <= fsm_init;
-      fsm_cond_7_2_2 <= 0;
-      fsm_cond_7_2_3 <= 0;
-      d3_fsm <= fsm_init;
-      fsm_cond_7_3_4 <= 0;
-      fsm_cond_7_3_5 <= 0;
-      fsm_cond_7_3_6 <= 0;
-      fsm_cond_8_1_7 <= 0;
-      fsm_cond_8_2_8 <= 0;
-      fsm_cond_8_2_9 <= 0;
-      fsm_cond_8_3_10 <= 0;
-      fsm_cond_8_3_11 <= 0;
-      fsm_cond_8_3_12 <= 0;
-      fsm_cond_9_1_13 <= 0;
-      fsm_cond_9_2_14 <= 0;
-      fsm_cond_9_2_15 <= 0;
-      fsm_cond_9_3_16 <= 0;
-      fsm_cond_9_3_17 <= 0;
-      fsm_cond_9_3_18 <= 0;
-      fsm_cond_10_1_19 <= 0;
-      fsm_cond_10_2_20 <= 0;
-      fsm_cond_10_2_21 <= 0;
-      fsm_cond_10_3_22 <= 0;
-      fsm_cond_10_3_23 <= 0;
-      fsm_cond_10_3_24 <= 0;
+      _d1_fsm <= fsm_init;
+      _fsm_cond_4_1_0 <= 0;
+      _fsm_cond_7_1_1 <= 0;
+      _d2_fsm <= fsm_init;
+      _fsm_cond_7_2_2 <= 0;
+      _fsm_cond_7_2_3 <= 0;
+      _d3_fsm <= fsm_init;
+      _fsm_cond_7_3_4 <= 0;
+      _fsm_cond_7_3_5 <= 0;
+      _fsm_cond_7_3_6 <= 0;
+      _fsm_cond_8_1_7 <= 0;
+      _fsm_cond_8_2_8 <= 0;
+      _fsm_cond_8_2_9 <= 0;
+      _fsm_cond_8_3_10 <= 0;
+      _fsm_cond_8_3_11 <= 0;
+      _fsm_cond_8_3_12 <= 0;
+      _fsm_cond_9_1_13 <= 0;
+      _fsm_cond_9_2_14 <= 0;
+      _fsm_cond_9_2_15 <= 0;
+      _fsm_cond_9_3_16 <= 0;
+      _fsm_cond_9_3_17 <= 0;
+      _fsm_cond_9_3_18 <= 0;
+      _fsm_cond_10_1_19 <= 0;
+      _fsm_cond_10_2_20 <= 0;
+      _fsm_cond_10_2_21 <= 0;
+      _fsm_cond_10_3_22 <= 0;
+      _fsm_cond_10_3_23 <= 0;
+      _fsm_cond_10_3_24 <= 0;
     end else begin
       count <= (count + 1);
-      d1_fsm <= fsm;
-      d2_fsm <= d1_fsm;
-      d3_fsm <= d2_fsm;
-      case(d3_fsm)
+      _d1_fsm <= fsm;
+      _d2_fsm <= _d1_fsm;
+      _d3_fsm <= _d2_fsm;
+      case(_d3_fsm)
         fsm_7: begin
-          if(fsm_cond_7_3_6) begin
+          if(_fsm_cond_7_3_6) begin
             valid <= 0;
           end 
         end
         fsm_8: begin
-          if(fsm_cond_8_3_12) begin
+          if(_fsm_cond_8_3_12) begin
             valid <= 0;
           end 
         end
         fsm_9: begin
-          if(fsm_cond_9_3_18) begin
+          if(_fsm_cond_9_3_18) begin
             valid <= 0;
           end 
         end
         fsm_10: begin
-          if(fsm_cond_10_3_24) begin
+          if(_fsm_cond_10_3_24) begin
             valid <= 0;
           end 
         end
       endcase
-      case(d2_fsm)
+      case(_d2_fsm)
         fsm_7: begin
-          if(fsm_cond_7_2_3) begin
+          if(_fsm_cond_7_2_3) begin
             valid <= 1;
           end 
-          fsm_cond_7_3_6 <= fsm_cond_7_3_5;
+          _fsm_cond_7_3_6 <= _fsm_cond_7_3_5;
         end
         fsm_8: begin
-          if(fsm_cond_8_2_9) begin
+          if(_fsm_cond_8_2_9) begin
             valid <= 1;
           end 
-          fsm_cond_8_3_12 <= fsm_cond_8_3_11;
+          _fsm_cond_8_3_12 <= _fsm_cond_8_3_11;
         end
         fsm_9: begin
-          if(fsm_cond_9_2_15) begin
+          if(_fsm_cond_9_2_15) begin
             valid <= 1;
           end 
-          fsm_cond_9_3_18 <= fsm_cond_9_3_17;
+          _fsm_cond_9_3_18 <= _fsm_cond_9_3_17;
         end
         fsm_10: begin
-          if(fsm_cond_10_2_21) begin
+          if(_fsm_cond_10_2_21) begin
             valid <= 1;
           end 
-          fsm_cond_10_3_24 <= fsm_cond_10_3_23;
+          _fsm_cond_10_3_24 <= _fsm_cond_10_3_23;
         end
       endcase
-      case(d1_fsm)
+      case(_d1_fsm)
         fsm_2: begin
           valid <= 0;
         end
         fsm_4: begin
-          if(fsm_cond_4_1_0) begin
+          if(_fsm_cond_4_1_0) begin
             valid <= 0;
           end 
         end
         fsm_7: begin
-          if(fsm_cond_7_1_1) begin
+          if(_fsm_cond_7_1_1) begin
             valid <= 1;
           end 
-          fsm_cond_7_2_3 <= fsm_cond_7_2_2;
-          fsm_cond_7_3_5 <= fsm_cond_7_3_4;
+          _fsm_cond_7_2_3 <= _fsm_cond_7_2_2;
+          _fsm_cond_7_3_5 <= _fsm_cond_7_3_4;
         end
         fsm_8: begin
-          if(fsm_cond_8_1_7) begin
+          if(_fsm_cond_8_1_7) begin
             valid <= 1;
           end 
-          fsm_cond_8_2_9 <= fsm_cond_8_2_8;
-          fsm_cond_8_3_11 <= fsm_cond_8_3_10;
+          _fsm_cond_8_2_9 <= _fsm_cond_8_2_8;
+          _fsm_cond_8_3_11 <= _fsm_cond_8_3_10;
         end
         fsm_9: begin
-          if(fsm_cond_9_1_13) begin
+          if(_fsm_cond_9_1_13) begin
             valid <= 1;
           end 
-          fsm_cond_9_2_15 <= fsm_cond_9_2_14;
-          fsm_cond_9_3_17 <= fsm_cond_9_3_16;
+          _fsm_cond_9_2_15 <= _fsm_cond_9_2_14;
+          _fsm_cond_9_3_17 <= _fsm_cond_9_3_16;
         end
         fsm_10: begin
-          if(fsm_cond_10_1_19) begin
+          if(_fsm_cond_10_1_19) begin
             valid <= 1;
           end 
-          fsm_cond_10_2_21 <= fsm_cond_10_2_20;
-          fsm_cond_10_3_23 <= fsm_cond_10_3_22;
+          _fsm_cond_10_2_21 <= _fsm_cond_10_2_20;
+          _fsm_cond_10_3_23 <= _fsm_cond_10_3_22;
         end
       endcase
       case(fsm)
@@ -244,7 +252,7 @@
           if((ready == 1)) begin
             valid <= 1;
           end 
-          fsm_cond_4_1_0 <= (ready == 1);
+          _fsm_cond_4_1_0 <= (ready == 1);
           if((ready == 1)) begin
             fsm <= fsm_5;
           end 
@@ -256,33 +264,33 @@
           fsm <= fsm_7;
         end
         fsm_7: begin
-          fsm_cond_7_1_1 <= ((count >= 16) && (ready == 1));
-          fsm_cond_7_2_2 <= ((count >= 16) && (ready == 1));
-          fsm_cond_7_3_4 <= ((count >= 16) && (ready == 1));
+          _fsm_cond_7_1_1 <= ((count >= 16) && (ready == 1));
+          _fsm_cond_7_2_2 <= ((count >= 16) && (ready == 1));
+          _fsm_cond_7_3_4 <= ((count >= 16) && (ready == 1));
           if(((count >= 16) && (ready == 1))) begin
             fsm <= fsm_8;
           end 
         end
         fsm_8: begin
-          fsm_cond_8_1_7 <= ((count >= 16) && (ready == 1));
-          fsm_cond_8_2_8 <= ((count >= 16) && (ready == 1));
-          fsm_cond_8_3_10 <= ((count >= 16) && (ready == 1));
+          _fsm_cond_8_1_7 <= ((count >= 16) && (ready == 1));
+          _fsm_cond_8_2_8 <= ((count >= 16) && (ready == 1));
+          _fsm_cond_8_3_10 <= ((count >= 16) && (ready == 1));
           if(((count >= 16) && (ready == 1))) begin
             fsm <= fsm_9;
           end 
         end
         fsm_9: begin
-          fsm_cond_9_1_13 <= ((count >= 16) && (ready == 1));
-          fsm_cond_9_2_14 <= ((count >= 16) && (ready == 1));
-          fsm_cond_9_3_16 <= ((count >= 16) && (ready == 1));
+          _fsm_cond_9_1_13 <= ((count >= 16) && (ready == 1));
+          _fsm_cond_9_2_14 <= ((count >= 16) && (ready == 1));
+          _fsm_cond_9_3_16 <= ((count >= 16) && (ready == 1));
           if(((count >= 16) && (ready == 1))) begin
             fsm <= fsm_10;
           end 
         end
         fsm_10: begin
-          fsm_cond_10_1_19 <= ((count >= 16) && (ready == 1));
-          fsm_cond_10_2_20 <= ((count >= 16) && (ready == 1));
-          fsm_cond_10_3_22 <= ((count >= 16) && (ready == 1));
+          _fsm_cond_10_1_19 <= ((count >= 16) && (ready == 1));
+          _fsm_cond_10_2_20 <= ((count >= 16) && (ready == 1));
+          _fsm_cond_10_3_22 <= ((count >= 16) && (ready == 1));
           if(((count >= 16) && (ready == 1))) begin
             fsm <= fsm_11;
           end 

sample/led/led.py

@@ -51,7 +51,7 @@ def mkTest():
 
     lib.simulation.setup_waveform(m, uut, m.get_vars())
     lib.simulation.setup_clock(m, clk, hperiod=5)
-    init = lib.simulation.setup_reset(m, rst, m.reset(), period=100)
+    init = lib.simulation.setup_reset(m, rst, m.make_reset(), period=100)
 
     init.add(
         Delay(1000 * 100),

sample/sort/sort.py

@@ -62,9 +62,9 @@ def chain_net(regs, fsm, e):
     # import assignment into always statement
     m.Always(Posedge(clk))(
         If(rst)(
-            *init
+            init
         ).Else(
-            fsm.to_case()
+            fsm.make_case()
         ))
 
     return m