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Yasuhiro Nitta
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merge develop branch
2 parents c7a4d8a + d5c3030 commit b9f19bc

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‎by_examples.ipynb‎

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{
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"cells": [
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"Veriloggen by examples\n",
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"====================\n"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"Empty Module\n",
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"--------------------"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 2,
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"metadata": {},
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"outputs": [
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{
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"name": "stdout",
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"output_type": "stream",
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"text": [
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"\n",
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"\n",
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"module empty\n",
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"(\n",
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" input CLK,\n",
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" input RST\n",
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");\n",
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"\n",
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"\n",
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"endmodule\n",
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"\n",
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"\n"
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]
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}
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],
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"source": [
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"from __future__ import absolute_import\n",
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"from __future__ import print_function\n",
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"from veriloggen import *\n",
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"\n",
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"m = Module('empty')\n",
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"clk = m.Input('CLK')\n",
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"rst = m.Input('RST')\n",
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"\n",
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"rtl = m.to_verilog()\n",
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"print(rtl)"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"Combinational Circuit\n",
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"--------------------"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"### Input/Output/Reg/Wire"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 14,
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"metadata": {},
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"outputs": [
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{
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"name": "stdout",
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"output_type": "stream",
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"text": [
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"\n",
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"\n",
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"module comb\n",
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"(\n",
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" input CLK,\n",
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" input RST,\n",
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" input a,\n",
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" output b\n",
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");\n",
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"\n",
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" reg c;\n",
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" wire d;\n",
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"\n",
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"endmodule\n",
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"\n",
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"\n"
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]
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}
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],
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"source": [
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"m = Module('comb')\n",
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"clk = m.Input('CLK')\n",
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"rst = m.Input('RST')\n",
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"\n",
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"a = m.Input('a')\n",
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"b = m.Output('b')\n",
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"c = m.Reg('c')\n",
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"d = m.Wire('d')\n",
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"\n",
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"rtl = m.to_verilog()\n",
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"print(rtl)"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"### Multi-bit signal"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 15,
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"metadata": {},
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"outputs": [
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{
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"name": "stdout",
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"output_type": "stream",
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"text": [
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"\n",
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"\n",
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"module comb\n",
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"(\n",
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" input CLK,\n",
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" input RST,\n",
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" input [8-1:0] a,\n",
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" output [8-1:0] b\n",
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");\n",
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"\n",
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" reg [16-1:0] c;\n",
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" wire [20-1:0] d;\n",
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"\n",
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"endmodule\n",
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"\n",
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"\n"
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]
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}
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],
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"source": [
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"m = Module('comb')\n",
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"clk = m.Input('CLK')\n",
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"rst = m.Input('RST')\n",
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"\n",
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"a = m.Input('a', 8)\n",
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"b = m.Output('b', width=a.width)\n",
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"c = m.Reg('c', 16)\n",
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"d = m.Wire('d', c.width + 4)\n",
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"\n",
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"rtl = m.to_verilog()\n",
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"print(rtl)"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"### Parameter and Localparam"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 16,
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"metadata": {},
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"outputs": [
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{
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"name": "stdout",
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"output_type": "stream",
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"text": [
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"\n",
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"\n",
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"module comb #\n",
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"(\n",
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" parameter sig_width = 8\n",
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")\n",
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"(\n",
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" input CLK,\n",
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" input RST,\n",
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" input [sig_width-1:0] a,\n",
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" output [sig_width-1:0] b\n",
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");\n",
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"\n",
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" reg [sig_width-1:0] c;\n",
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" wire [sig_width+4-1:0] d;\n",
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"\n",
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"endmodule\n",
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"\n",
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"\n"
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]
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}
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],
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"source": [
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"m = Module('comb')\n",
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"clk = m.Input('CLK')\n",
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"rst = m.Input('RST')\n",
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"\n",
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"sig_width = m.Parameter('sig_width', 8)\n",
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"\n",
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"a = m.Input('a', sig_width)\n",
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"b = m.Output('b', a.width)\n",
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"c = m.Reg('c', a.width)\n",
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"d = m.Wire('d', c.width + 4)\n",
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"\n",
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"rtl = m.to_verilog()\n",
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"print(rtl)"
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]
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},
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{
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"cell_type": "markdown",
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"metadata": {},
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"source": [
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"### Substitution and Assign"
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]
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},
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{
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"cell_type": "code",
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"execution_count": 21,
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"metadata": {},
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"outputs": [
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{
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"data": {
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"text/plain": [
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"<veriloggen.core.vtypes.Subst at 0x10c721ad0>"
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]
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},
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"execution_count": 21,
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"metadata": {},
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"output_type": "execute_result"
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}
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],
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"source": [
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"m = Module('comb')\n",
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"clk = m.Input('CLK')\n",
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"rst = m.Input('RST')\n",
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"\n",
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"a = m.Input('a', 8)\n",
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"b = m.Output('b', 8)\n",
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"c = m.Wire('c', 8)\n",
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"d = m.Wire('d', 8)\n",
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"\n",
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"# Substitusion\n",
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"c(a + 1) # --> Subst object representing \"c <- a + 1\""
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]
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},
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{
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"cell_type": "code",
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"execution_count": 25,
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"metadata": {},
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"outputs": [
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{
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"name": "stdout",
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"output_type": "stream",
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"text": [
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"\n",
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"\n",
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"module comb\n",
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"(\n",
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" input CLK,\n",
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" input RST,\n",
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" input [8-1:0] a,\n",
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" output [8-1:0] b\n",
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");\n",
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"\n",
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" wire [8-1:0] c;\n",
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" wire [8-1:0] d;\n",
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" assign c = a + 1;\n",
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" assign d = a + 2;\n",
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"\n",
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"endmodule\n",
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"\n",
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"\n"
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]
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}
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],
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"source": [
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"m = Module('comb')\n",
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"clk = m.Input('CLK')\n",
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"rst = m.Input('RST')\n",
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"\n",
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"a = m.Input('a', 8)\n",
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"b = m.Output('b', 8)\n",
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"c = m.Wire('c', 8)\n",
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"d = m.Wire('d', 8)\n",
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"\n",
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"# Assign requires Substitution object\n",
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"m.Assign(c(a + 1))\n",
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"\n",
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"# var.assign() method returns same result\n",
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"d.assign(a + 2)\n",
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"\n",
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"rtl = m.to_verilog()\n",
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"print(rtl)"
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]
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}
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],
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"metadata": {
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"kernelspec": {
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"display_name": "Python 3",
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"language": "python",
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"name": "python3"
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},
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"language_info": {
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"codemirror_mode": {
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"name": "ipython",
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"version": 3
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},
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"file_extension": ".py",
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"mimetype": "text/x-python",
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"name": "python",
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"nbconvert_exporter": "python",
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"pygments_lexer": "ipython3",
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"version": "3.7.5"
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}
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},
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"nbformat": 4,
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"nbformat_minor": 2
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}

‎tests/extension/stream_/average/test_stream_average.py‎

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reg signed [32-1:0] __delay_data_31;
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reg signed [32-1:0] _plus_data_25;
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reg signed [32-1:0] __delay_data_32;
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reg signed [32-1:0] _sra_data_26;
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reg signed [32-1:0] __delay_data_33;
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wire signed [32-1:0] _sra_data_26;
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assign _sra_data_26 = _plus_data_25 >>> 3'sd3;
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reg signed [32-1:0] _plus_data_28;
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assign zdata = _plus_data_28;
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__delay_data_31 <= 0;
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_plus_data_25 <= 0;
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__delay_data_32 <= 0;
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_sra_data_26 <= 0;
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__delay_data_33 <= 0;
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_plus_data_28 <= 0;
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end else begin
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_plus_data_2 <= xdata + 1'sd0;
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__delay_data_31 <= __delay_data_30;
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_plus_data_25 <= _plus_data_21 + _plus_data_24;
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__delay_data_32 <= __delay_data_31;
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_sra_data_26 <= _plus_data_25 >>> 3'sd3;
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__delay_data_33 <= __delay_data_32;
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_plus_data_28 <= _sra_data_26 + __delay_data_33;
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_plus_data_28 <= _sra_data_26 + __delay_data_32;
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end
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end
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