Merge branch 'develop' into feature_axi_stream

Author: shtaxxx

tests/extension/thread_/stream_counter_offset/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

tests/extension/thread_/stream_counter_offset/test_thread_stream_counter_offset.py

@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_stream_counter_offset
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_stream_counter_offset.run(filename=None, simtype=simtype,
+                                            outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')

tests/extension/thread_/stream_counter_offset/thread_stream_counter_offset.py

@@ -0,0 +1,145 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    datawidth = 32
+    addrwidth = 10
+    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
+    ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
+    ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
+    ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
+
+    strm = vthread.Stream(m, 'mystream', clk, rst)
+    a = strm.source('a')
+    b = strm.source('b')
+    x = strm.Counter(initval=6, offset=2, size=8)
+    c = a + b - a - b + x
+    strm.sink(c, 'c')
+
+    def comp_stream(size, offset):
+        strm.set_source('a', ram_a, offset, size)
+        strm.set_source('b', ram_b, offset, size)
+        strm.set_sink('c', ram_c, offset, size)
+        strm.run()
+        strm.join()
+
+    def comp_sequential(size, offset):
+        sum = 0
+        x = 6
+        for i in range(size):
+            a = ram_a.read(i + offset)
+            b = ram_b.read(i + offset)
+            sum = a + b - a - b + x
+            ram_c.write(i + offset, sum)
+            x += 1
+            if x == 8:
+                x = 2
+
+    def check(size, offset_stream, offset_seq):
+        all_ok = True
+        for i in range(size):
+            st = ram_c.read(i + offset_stream)
+            sq = ram_c.read(i + offset_seq)
+            if vthread.verilog.NotEql(st, sq):
+                all_ok = False
+        if all_ok:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+    def comp(size):
+        # stream
+        offset = 0
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        comp_stream(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024, size)
+
+        # sequential
+        offset = size
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        comp_sequential(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024 * 2, size)
+
+        # verification
+        check(size, 0, offset)
+
+        vthread.finish()
+
+    th = vthread.Thread(m, 'th_comp', clk, rst, comp)
+    fsm = th.start(32)
+
+    return m
+
+
+def mkTest(memimg_name=None):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
+    memory.connect(ports, 'myaxi')
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    #simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    sim = simulation.Simulator(test, sim=simtype)
+    rslt = sim.run(outputfile=outputfile)
+    lines = rslt.splitlines()
+    if simtype == 'verilator' and lines[-1].startswith('-'):
+        rslt = '\n'.join(lines[:-1])
+    return rslt
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)

veriloggen/stream/graph.py

@@ -217,6 +217,8 @@ def visit__Accumulator(self, node):
         if node.interval is not None:
             interval = self.visit(node.interval)
         initval = self.visit(node.initval)
+        if node.offset is not None:
+            offset = self.visit(node.offset)
         if node.dependency is not None:
             dependency = self.visit(node.dependency)
         if node.enable is not None:
@@ -229,6 +231,8 @@ def visit__Accumulator(self, node):
         if node.interval is not None:
             self.graph.add_edge(interval, node, label='interval')
         self.graph.add_edge(initval, node, label='initval')
+        if node.offset is not None:
+            self.graph.add_edge(offset, node, label='offset')
         if node.dependency is not None:
             self.graph.add_edge(dependency, node, label='dependency')
         if node.enable is not None:

veriloggen/stream/scheduler.py

@@ -125,6 +125,8 @@ def visit__Accumulator(self, node):
         interval = (self.visit(node.interval)
                     if node.interval is not None else None)
         initval = self.visit(node.initval)
+        offset = (self.visit(node.offset)
+                  if node.offset is not None else None)
         dependency = (self.visit(node.dependency)
                       if node.dependency is not None else None)
         enable = self.visit(node.enable) if node.enable is not None else None
@@ -136,6 +138,8 @@ def visit__Accumulator(self, node):
         if node.interval is not None:
             node.interval = self.fill_gap(node.interval, mine)
         node.initval = self.fill_gap(node.initval, mine)
+        if node.offset is not None:
+            node.offset = self.fill_gap(node.offset, mine)
         if node.enable is not None:
             node.enable = self.fill_gap(node.enable, mine)
         if node.reset is not None:

veriloggen/stream/stypes.py

@@ -2465,13 +2465,15 @@ class _Accumulator(_UnaryOperator):
     latency = 1
     ops = (vtypes.Plus, )
 
-    def __init__(self, right, size=None, interval=None, initval=None,
+    def __init__(self, right, size=None, interval=None, initval=None, offset=None,
                  dependency=None, enable=None, reset=None, width=32, signed=True):
 
         self.size = _to_constant(size) if size is not None else None
         self.interval = _to_constant(interval) if interval is not None else None
         self.initval = (_to_constant(initval)
                         if initval is not None else _to_constant(0))
+        self.offset = (_to_constant(offset)
+                       if offset is not None else None)
 
         if not isinstance(self.initval, _Constant):
             raise TypeError("initval must be Constant, not '%s'" %
@@ -2664,8 +2666,9 @@ class ReduceAdd(_Accumulator):
 
     def __init__(self, right, size=None, interval=None, initval=0,
                  enable=None, reset=None, width=32, signed=True):
+        offset = None
         dependency = None
-        _Accumulator.__init__(self, right, size, interval, initval,
+        _Accumulator.__init__(self, right, size, interval, initval, offset,
                               dependency, enable, reset, width, signed)
         self.graph_label = 'ReduceAdd'
 
@@ -2675,8 +2678,9 @@ class ReduceSub(_Accumulator):
 
     def __init__(self, right, size=None, interval=None, initval=0,
                  enable=None, reset=None, width=32, signed=True):
+        offset = None
         dependency = None
-        _Accumulator.__init__(self, right, size, interval, initval,
+        _Accumulator.__init__(self, right, size, interval, initval, offset,
                               dependency, enable, reset, width, signed)
         self.graph_label = 'ReduceSub'
 
@@ -2687,8 +2691,9 @@ class ReduceMul(_Accumulator):
 
     def __init__(self, right, size=None, interval=None, initval=0,
                  enable=None, reset=None, width=32, signed=True):
+        offset = None
         dependency = None
-        _Accumulator.__init__(self, right, size, interval, initval,
+        _Accumulator.__init__(self, right, size, interval, initval, offset,
                               dependency, enable, reset, width, signed)
         self.graph_label = 'ReduceMul'
 
@@ -2700,8 +2705,9 @@ class ReduceDiv(_Accumulator):
     def __init__(self, right, size=None, interval=None, initval=0,
                  enable=None, reset=None, width=32, signed=True):
         raise NotImplementedError()
+        offset = None
         dependency = None
-        _Accumulator.__init__(self, right, size, interval, initval,
+        _Accumulator.__init__(self, right, size, interval, initval, offset,
                               dependency, enable, reset, width, signed)
         self.graph_label = 'ReduceDiv'
 
@@ -2711,8 +2717,9 @@ class ReduceMax(_Accumulator):
 
     def __init__(self, right, size=None, interval=None, initval=0,
                  enable=None, reset=None, width=32, signed=True):
+        offset = None
         dependency = None
-        _Accumulator.__init__(self, right, size, interval, initval,
+        _Accumulator.__init__(self, right, size, interval, initval, offset,
                               dependency, enable, reset, width, signed)
         self.graph_label = 'ReduceMax'
 
@@ -2722,8 +2729,9 @@ class ReduceMin(_Accumulator):
 
     def __init__(self, right, size=None, interval=None, initval=0,
                  enable=None, reset=None, width=32, signed=True):
+        offset = None
         dependency = None
-        _Accumulator.__init__(self, right, size, interval, initval,
+        _Accumulator.__init__(self, right, size, interval, initval, offset,
                               dependency, enable, reset, width, signed)
         self.graph_label = 'ReduceMin'
 
@@ -2732,8 +2740,9 @@ class ReduceCustom(_Accumulator):
 
     def __init__(self, ops, right, size=None, interval=None, initval=0,
                  enable=None, reset=None, width=32, signed=True, label=None):
+        offset = None
         dependency = None
-        _Accumulator.__init__(self, right, size, interval, initval,
+        _Accumulator.__init__(self, right, size, interval, initval, offset,
                               dependency, enable, reset, width, signed)
         if not isinstance(ops, (tuple, list)):
             ops = tuple([ops])
@@ -2743,10 +2752,10 @@ def __init__(self, ops, right, size=None, interval=None, initval=0,
 
 class Counter(_Accumulator):
 
-    def __init__(self, size=None, step=1, interval=None, initval=0,
+    def __init__(self, size=None, step=1, interval=None, initval=0, offset=None,
                  dependency=None, enable=None, reset=None, width=32, signed=False):
 
-        _Accumulator.__init__(self, step, size, interval, initval,
+        _Accumulator.__init__(self, step, size, interval, initval, offset,
                               dependency, enable, reset, width, signed)
         self.graph_label = 'Counter'
 
@@ -2759,6 +2768,7 @@ def _implement(self, m, seq, svalid=None, senable=None):
         interval_data = self.interval.sig_data if self.interval is not None else None
 
         initval_data = self.initval.sig_data
+        offset_data = self.offset.sig_data if self.offset is not None else None
         width = self.bit_length()
         signed = self.get_signed()
 
@@ -2770,7 +2780,10 @@ def _implement(self, m, seq, svalid=None, senable=None):
                       initval=initval_data, signed=signed)
 
         next_count_value = count + step
-        if self.size is not None:
+        if self.size is not None and self.offset is not None:
+            next_count_value = vtypes.Mux(count >= size_data - step,
+                                          offset_data, next_count_value)
+        elif self.size is not None:
             next_count_value = vtypes.Mux(count >= size_data - step,
                                           next_count_value - size_data, next_count_value)
 
@@ -2835,10 +2848,11 @@ def __init__(self, size, interval=None,
             right = dependency
 
         initval = 0
+        offset = None
         width = 1
         signed = False
 
-        _Accumulator.__init__(self, right, size, interval, initval,
+        _Accumulator.__init__(self, right, size, interval, initval, offset,
                               dependency, enable, reset, width, signed)
         self.graph_label = 'Pulse'
 
@@ -2911,10 +2925,10 @@ def ReduceCustomValid(ops, right, size, interval=None, initval=0,
     return data, valid
 
 
-def CounterValid(size, step=1, interval=None, initval=0,
+def CounterValid(size, step=1, interval=None, initval=0, offset=None,
                  dependency=None, enable=None, reset=None, width=32, signed=False):
 
-    data = Counter(size, step, interval, initval,
+    data = Counter(size, step, interval, initval, offset,
                    dependency, enable, reset, width, signed)
     valid = Pulse(size, dependency=dependency, enable=enable, reset=reset)