Fixed some simple typos.

Author: shtaxxx

veriloggen/core/vtypes.py

@@ -498,9 +498,9 @@ def dec(self):
 class AnyType(_Variable): pass
 
 #-------------------------------------------------------------------------------
-class _ParameterVairable(_Variable):
+class _ParameterVariable(_Variable):
     def __init__(self, value, width=None, signed=False, name=None, module=None):
-        if isinstance(value, _ParameterVairable):
+        if isinstance(value, _ParameterVariable):
             value = value.value
         _Variable.__init__(self, width=width, signed=signed, value=value, name=name,
                            module=module)
@@ -510,9 +510,9 @@ def bit_length(self):
             return 32
         return self.width
 
-class Parameter(_ParameterVairable): pass
-class Localparam(_ParameterVairable): pass
-class Supply(_ParameterVairable): pass
+class Parameter(_ParameterVariable): pass
+class Localparam(_ParameterVariable): pass
+class Supply(_ParameterVariable): pass
 
 #-------------------------------------------------------------------------------
 class _Constant(_Numeric):

veriloggen/fsm/fsm.py

@@ -498,7 +498,7 @@ def _add_delayed_subst(self, subst, index, delay):
         left = subst.left
         right = subst.right
         if isinstance(right, (bool, int, float, str,
-                              vtypes._Constant, vtypes._ParameterVairable)):
+                              vtypes._Constant, vtypes._ParameterVariable)):
             return subst
         width = left.bit_length()
         prev = right

veriloggen/seq/seq.py

@@ -452,7 +452,7 @@ def _add_delayed_subst(self, subst, delay):
         left = subst.left
         right = subst.right
         if isinstance(right, (bool, int, float, str,
-                              vtypes._Constant, vtypes._ParameterVairable)):
+                              vtypes._Constant, vtypes._ParameterVariable)):
             return subst
         width = left.bit_length()
         prev = right