memimg_name with tempfile

Author: shtaxxx

examples/thread_embedded_verilog_ipxact/test_thread_embedded_verilog_ipxact.py

@@ -228,7 +228,7 @@
   reg [8-1:0] _memory_mem [0:2**20-1];
 
   initial begin
-    $readmemh("_memory_memimg_.out", _memory_mem);
+    $readmemh("memimg_thread_embedded_verilog_ipxact.out", _memory_mem);
   end
 
   reg [33-1:0] _write_count;
@@ -2878,7 +2878,10 @@
 
 def test():
     veriloggen.reset()
-    test_module = thread_embedded_verilog_ipxact.mkTest()
+
+    memimg_name = 'memimg_thread_embedded_verilog_ipxact.out'
+
+    test_module = thread_embedded_verilog_ipxact.mkTest(memimg_name=memimg_name)
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser

examples/thread_embedded_verilog_ipxact/thread_embedded_verilog_ipxact.py

@@ -82,7 +82,7 @@ def copy(copy_bytes, src_offset, dst_offset):
     return m
 
 
-def mkTest():
+def mkTest(memimg_name=None):
     m = Module('test')
 
     copy_bytes = 1024 * 4
@@ -94,7 +94,8 @@ def mkTest():
     clk = uut['CLK']
     rst = uut['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst,
+                                memimg_name=memimg_name)
     memory.connect(uut.get_inst_ports(), 'maxi')
 
     # AXI-Slave controller
@@ -159,7 +160,10 @@ def ctrl():
 
 
 if __name__ == '__main__':
-    test = mkTest()
+
+    memimg_name = 'memimg_thread_embedded_verilog_ipxact.out'
+
+    test = mkTest(memimg_name=memimg_name)
     verilog = test.to_verilog('tmp.v')
     print(verilog)
 

examples/thread_memcpy_ipxact_ultra96v2_pynq/test_thread_memcpy_ipxact.py

@@ -226,7 +226,7 @@
   reg [8-1:0] _memory_mem [0:2**20-1];
 
   initial begin
-    $readmemh("_memory_memimg_.out", _memory_mem);
+    $readmemh("memimg_thread_embedded_verilog_ipxact.out", _memory_mem);
   end
 
   reg [33-1:0] _write_count;
@@ -2861,7 +2861,10 @@
 
 def test():
     veriloggen.reset()
-    test_module = thread_memcpy_ipxact.mkTest()
+
+    memimg_name = 'memimg_thread_embedded_verilog_ipxact.out'
+
+    test_module = thread_memcpy_ipxact.mkTest(memimg_name=memimg_name)
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser

examples/thread_memcpy_ipxact_ultra96v2_pynq/thread_memcpy_ipxact.py

@@ -65,7 +65,7 @@ def copy(copy_bytes, src_offset, dst_offset):
     return m
 
 
-def mkTest():
+def mkTest(memimg_name=None):
     m = Module('test')
 
     copy_bytes = 1024 * 4
@@ -77,7 +77,8 @@ def mkTest():
     clk = uut['CLK']
     rst = uut['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst,
+                                memimg_name=memimg_name)
     memory.connect(uut.get_inst_ports(), 'maxi')
 
     # AXI-Slave controller
@@ -142,7 +143,10 @@ def ctrl():
 
 
 if __name__ == '__main__':
-    test = mkTest()
+
+    memimg_name = 'memimg_thread_memcpy_ipxact.out'
+
+    test = mkTest(memimg_name=memimg_name)
     verilog = test.to_verilog('tmp.v')
     print(verilog)
 

examples/thread_uart_top_nexys4/thread_uart_top.py

@@ -96,7 +96,8 @@ def mkTest(baudrate=19200, clockfreq=19200 * 10):
     rx.assign(txd)
     rxd.assign(tx)
 
-    simulation.setup_waveform(m, uut, uart_tx, uart_rx)
+    vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
+    simulation.setup_waveform(m, uut, uart_tx, uart_rx, dumpfile=vcd_name)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
 

examples/thread_verilog_submodule_ipxact/test_thread_verilog_submodule_ipxact.py

@@ -228,7 +228,7 @@
   reg [8-1:0] _memory_mem [0:2**20-1];
 
   initial begin
-    $readmemh("_memory_memimg_.out", _memory_mem);
+    $readmemh("memimg_thread_verilog_submodule_ipxact.out", _memory_mem);
   end
 
   reg [33-1:0] _write_count;
@@ -3047,7 +3047,10 @@
 
 def test():
     veriloggen.reset()
-    test_module = thread_verilog_submodule_ipxact.mkTest()
+
+    memimg_name = 'memimg_thread_verilog_submodule_ipxact.out'
+
+    test_module = thread_verilog_submodule_ipxact.mkTest(memimg_name=memimg_name)
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser

examples/thread_verilog_submodule_ipxact/thread_verilog_submodule_ipxact.py

@@ -175,7 +175,7 @@ def copy(copy_bytes, src_offset, dst_offset):
     return m
 
 
-def mkTest():
+def mkTest(memimg_name=None):
     m = Module('test')
 
     copy_bytes = 1024 * 4
@@ -187,7 +187,8 @@ def mkTest():
     clk = uut['CLK']
     rst = uut['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst,
+                                memimg_name=memimg_name)
     memory.connect(uut.get_inst_ports(), 'maxi')
 
     # AXI-Slave controller
@@ -252,7 +253,10 @@ def ctrl():
 
 
 if __name__ == '__main__':
-    test = mkTest()
+
+    memimg_name = 'memimg_thread_verilog_submodule_ipxact.out'
+
+    test = mkTest(memimg_name=memimg_name)
     verilog = test.to_verilog('tmp.v')
     print(verilog)
 

tests/extension/types_/ipxact_/master/test_types_ipxact_master.py

@@ -143,7 +143,7 @@
   reg [8-1:0] _memory_mem [0:2**20-1];
 
   initial begin
-    $readmemh("_memory_memimg_.out", _memory_mem);
+    $readmemh("memimg_types_ipxact_master.out", _memory_mem);
   end
 
   reg [33-1:0] _write_count;
@@ -986,7 +986,10 @@
 
 def test():
     veriloggen.reset()
-    test_module = types_ipxact_master.mkTest()
+
+    memimg_name = 'memimg_types_ipxact_master.out'
+
+    test_module = types_ipxact_master.mkTest(memimg_name=memimg_name)
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser

veriloggen/types/axi.py

@@ -2,8 +2,10 @@
 from __future__ import print_function
 from __future__ import division
 
+import os
 import functools
 import math
+import tempfile
 from collections import defaultdict
 
 import veriloggen.core.vtypes as vtypes
@@ -2344,7 +2346,8 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
 
         if memimg is None:
             if memimg_name is None:
-                memimg_name = '_'.join(['', self.name, 'memimg', '.out'])
+                memimg_name = get_memimg_name()
+
             size = 2 ** self.mem_addrwidth
             width = self.mem_datawidth
             self._make_img(memimg_name, size, width)
@@ -2361,7 +2364,7 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
             if memimg_datawidth is None:
                 memimg_datawidth = mem_datawidth
             if memimg_name is None:
-                memimg_name = '_'.join(['', self.name, 'memimg', '.out'])
+                memimg_name = get_memimg_name()
 
             num_words = to_memory_image(memimg_name, memimg, datawidth=memimg_datawidth)
             # resize mem_addrwidth according to the memimg size
@@ -2893,7 +2896,8 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, numports=2,
 
         if memimg is None:
             if memimg_name is None:
-                memimg_name = '_'.join(['', self.name, 'memimg', '.out'])
+                memimg_name = get_memimg_name()
+
             size = 2 ** self.mem_addrwidth
             width = self.mem_datawidth
             self._make_img(memimg_name, size, width)
@@ -2910,7 +2914,7 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, numports=2,
             if memimg_datawidth is None:
                 memimg_datawidth = mem_datawidth
             if memimg_name is None:
-                memimg_name = '_'.join(['', self.name, 'memimg', '.out'])
+                memimg_name = get_memimg_name()
 
             num_words = to_memory_image(memimg_name, memimg, datawidth=memimg_datawidth)
             # resize mem_addrwidth according to the memimg size
@@ -3371,7 +3375,7 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
 
         if memimg is None:
             if memimg_name is None:
-                memimg_name = '_'.join(['', self.name, 'memimg', '.out'])
+                memimg_name = get_memimg_name()
             size = 2 ** self.mem_addrwidth
             width = self.mem_datawidth
             self._make_img(memimg_name, size, width)
@@ -3388,7 +3392,7 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
             if memimg_datawidth is None:
                 memimg_datawidth = mem_datawidth
             if memimg_name is None:
-                memimg_name = '_'.join(['', self.name, 'memimg', '.out'])
+                memimg_name = get_memimg_name()
 
             num_words = to_memory_image(memimg_name, memimg, datawidth=memimg_datawidth)
             # resize mem_addrwidth according to the memimg size
@@ -3768,7 +3772,7 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, numports=2,
 
         if memimg is None:
             if memimg_name is None:
-                memimg_name = '_'.join(['', self.name, 'memimg', '.out'])
+                memimg_name = get_memimg_name()
             size = 2 ** self.mem_addrwidth
             width = self.mem_datawidth
             self._make_img(memimg_name, size, width)
@@ -3785,7 +3789,7 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32, numports=2,
             if memimg_datawidth is None:
                 memimg_datawidth = mem_datawidth
             if memimg_name is None:
-                memimg_name = '_'.join(['', self.name, 'memimg', '.out'])
+                memimg_name = get_memimg_name()
 
             num_words = to_memory_image(memimg_name, memimg, datawidth=memimg_datawidth)
             # resize mem_addrwidth according to the memimg size
@@ -4363,3 +4367,12 @@ def split_read_write(m, ports, prefix,
         w_ports[w_name] = w_port
 
     return r_ports, w_ports
+
+
+def get_memimg_name():
+    memimg_fd = tempfile.NamedTemporaryFile(prefix="memimg_",
+                                            suffix=".out",
+                                            dir=os.getcwd(),
+                                            delete=False)
+    memimg_name = memimg_fd.name
+    return memimg_name