@@ -3103,28 +3103,29 @@ def eval(self):
31033103
31043104 def _implement (self , m , seq , svalid = None , senable = None ):
31053105 width = self .bit_length ()
3106+ point = self .get_point ()
31063107 signed = self .get_signed ()
31073108 rdata = self .right .sig_data
31083109
31093110 self .valid = svalid
31103111 self .enable = senable
31113112
31123113 if self .latency == 0 :
3113- data = m . Wire ( self .name ('data' ), width , signed = signed )
3114+ data = fx . FixedWire ( m , self .name ('data' ), width , point , signed = signed )
31143115 data .assign (rdata )
31153116 self .sig_data = data
31163117
31173118 elif self .latency == 1 :
3118- data = m . Reg ( self .name ('data' ), width , initval = 0 , signed = signed )
3119+ data = fx . FixedReg ( m , self .name ('data' ), width , point , initval = 0 , signed = signed )
31193120 self .sig_data = data
31203121 seq (data (rdata ), cond = senable )
31213122
31223123 else :
31233124 prev_data = None
31243125
31253126 for i in range (self .latency ):
3126- data = m .Reg (self .name ('data_d%d' % i ),
3127- width , initval = 0 , signed = signed )
3127+ data = fx .Reg (m , self .name ('data_d%d' % i ),
3128+ width , point , initval = 0 , signed = signed )
31283129 if i == 0 :
31293130 seq (data (self .op (rdata )), cond = senable )
31303131 else :
@@ -3163,12 +3164,13 @@ def eval(self):
31633164
31643165 def _implement (self , m , seq , svalid = None , senable = None ):
31653166 width = self .bit_length ()
3167+ point = self .get_point ()
31663168 signed = self .get_signed ()
31673169
31683170 self .valid = svalid
31693171 self .enable = senable
31703172
3171- data = m . Reg ( self .name ('data' ), width , initval = 0 , signed = signed )
3173+ data = fx . FixedReg ( m , self .name ('data' ), width , point , initval = 0 , signed = signed )
31723174 self .sig_data = data
31733175
31743176 def write (self , fsm , value ):
@@ -3204,11 +3206,12 @@ def _implement(self, m, seq, svalid=None, senable=None):
32043206 (self .latency , 1 ))
32053207
32063208 width = self .bit_length ()
3209+ point = self .get_point ()
32073210 signed = self .get_signed ()
32083211
32093212 arg_data = [arg .sig_data for arg in self .args ]
32103213
3211- data = m . Reg ( self .name ('data' ), width , initval = 0 , signed = signed )
3214+ data = fx . FixedReg ( m , self .name ('data' ), width , point , initval = 0 , signed = signed )
32123215 self .sig_data = data
32133216
32143217 when_cond = self .args [1 ].sig_data if len (self .args ) == 2 else None
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