lib.FSM is upgraded.

Author: shtaxxx

sample/bram/bram.py

@@ -72,29 +72,28 @@ def mkTop():
 
     m.Instance(mkBram('my_'), 'inst_bram', params, ports)
 
+    # FSM definition
     fsm = lib.FSM(m, 'fsm')
     init = fsm.get_index()
-    fsmbody = []
-    fsmbody.append(
-            fsm( bramif.addr(0), bramif.datain(0), bramif.write(0), fsm.next() ))
+    
+    fsm( bramif.addr(0), bramif.datain(0), bramif.write(0), fsm.next() )
     first = fsm.get_index()
-    fsmbody.append(
-            fsm( bramif.datain(bramif.datain + 4), fsm.next() ))
-    fsmbody.append(
-            fsm( bramif.write(0), fsm.next() ))
-    fsmbody.append(
-            fsm( 
-                If(bramif.addr == 128)(
-                    bramif.addr(0), fsm.goto(init)
-                ).Else(
-                    bramif.addr(bramif.addr + 1), fsm.goto(first)
-                )))
+    
+    fsm( bramif.datain(bramif.datain + 4), fsm.next() )
+    fsm( bramif.write(0), fsm.next() )
+    fsm( 
+        If(bramif.addr == 128)(
+            bramif.addr(0), fsm.goto(init)
+        ).Else(
+            bramif.addr(bramif.addr + 1), fsm.goto(first)
+        ))
 
     m.Always(Posedge(clk))(
         If(rst)(
             bramif.addr(0), bramif.datain(0), bramif.write(0), fsm.init()
         ).Else(
-            *fsmbody
+            # inserting FSM body
+            *fsm.get_all()
         ))
 
     return m

sample/long-fsm/Makefile

@@ -0,0 +1,25 @@
+TARGET=led.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: run
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v

sample/long-fsm/led.py

@@ -0,0 +1,32 @@
+import sys
+import os
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', width)
+
+    fsm = lib.FSM(m, 'fsm')
+    init = fsm.get_index()
+    for i in range(1023):
+        fsm( fsm.next() )
+    fsm( led(led + 1), fsm.goto(init) )
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            led(0),
+            fsm.init()
+        ).Else(
+            *fsm.get_all()
+        ))
+    
+    return m
+
+if __name__ == '__main__':
+    led = mkLed()
+    # led.to_verilog(filename='tmp.v')
+    verilog = led.to_verilog()
+    print(verilog)

sample/long-fsm/veriloggen

@@ -0,0 +1 @@
+../../veriloggen

sample/test/lib-fsm/led.py

@@ -15,20 +15,18 @@ def mkLed():
     # get the initial index (= 0)
     init = fsm.get_index()
 
-    fsm_body = []
-    fsm_body.append( fsm(count(count + 1), fsm.next()) )
-    fsm_body.append( fsm(count(count + 2), fsm.next()) )
+    fsm(count(count + 1), fsm.next())
+    fsm(count(count + 2), fsm.next())
 
     # get the current index (= 2)
     here = fsm.get_index()
-    
-    fsm_body.append( fsm(count(count + 3), fsm.next()) )
-    
+    fsm(count(count + 3), fsm.next())
+
     # jump by using label "init"
-    fsm_body.append( fsm(If(count < 1024)( fsm.goto(init) ).Else( fsm.next() )) )
+    fsm(If(count < 1024)( fsm.goto(init) ).Else( fsm.next() ))
 
     # jump by using label "here"
-    fsm_body.append( fsm(led(led + 1), fsm.goto(here)) )
+    fsm(led(led + 1), fsm.goto(here))
 
     m.Always(Posedge(clk))(
         If(rst)(
@@ -37,7 +35,7 @@ def mkLed():
             fsm.init()
         ).Else(
             # inserting the FSM body
-            *fsm_body
+            *fsm.get_all()
         ))
 
     return m

veriloggen/lib.py

@@ -1,3 +1,4 @@
+import collections
 import vtypes
 
 #-------------------------------------------------------------------------------
@@ -8,26 +9,29 @@ def __init__(self, m, name, width=32, initname='init'):
         self.name = name
         self.state = self.m.Reg(name, width)
         self.state_count = 0
-        self.mark = {}
+        self.mark = collections.OrderedDict()
         self.set_mark(0, self.name + '_' + initname)
+        self.body = collections.OrderedDict()
 
-    def get_index(self):
-        return self.state_count
-        
     def init(self):
         return self.goto(0)
 
     def next(self):
-        index = self.state_count + 1
+        index = self.get_index() + 1
         if index not in self.mark:
             self.set_mark(index)
         return self.state( self.mark[index] )
 
     def goto(self, index):
+        if isinstance(index, vtypes.Localparam):
+            index = self.get_mark_index(index)
         if index not in self.mark:
             self.set_mark(index)
         return self.state( self.mark[index] )
 
+    def get_index(self):
+        return self.state_count
+        
     def set_mark(self, index=None, name=None):
         if index is None:
             index = self.state_count
@@ -38,21 +42,45 @@ def set_mark(self, index=None, name=None):
     def get_mark(self, index=None):
         if index is None:
             index = self.state_count
+        if index not in self.mark:
+            raise KeyError("No such index in FSM marks: %s" % index)
         return self.mark[index]
-        
-    def cond(self):
-        ret = (self.state == self.mark[self.state_count])
-        self.state_count += 1
+
+    def get_mark_index(self, s):
+        for index, m in self.mark.items():
+            if m.name == s.name:
+                return index
+        raise KeyError("No such mark in FSM marks: %s" % s.name)
+    
+    def add(self, *statement):
+        index = self.get_index()
+        self.body[index] = statement # tuple
+        self.update_state()
+        ret = self.get(index)
         return ret
 
-    def add_stage(self, *statement):
-        return vtypes.If(self.cond())( *statement )
+    def get(self, index):
+        return vtypes.If(self.cond(index))( *self.body[index] ) # tuple
+    
+    def get_all(self):
+        ret = []
+        for index in self.body.keys():
+            ret.append(self.get(index))
+        return tuple(ret)
 
+    def update_state(self):
+        self.state_count += 1
+        
+    def cond(self, index):
+        if index not in self.mark:
+            self.set_mark(index)
+        return (self.state == self.mark[index])
+
     def __call__(self, *statement):
-        return self.add_stage(*statement)
+        return self.add(*statement)
 
     def __getitem__(self, index):
-        return self.mark[index]
+        return self.body[index]
 
     def __len__(self):
         return self.state_count + 1

veriloggen/vtypes.py

@@ -62,12 +62,13 @@ def __getitem__(self, r):
 
 #-------------------------------------------------------------------------------
 class _Variable(_Numeric):
-    def __init__(self, name, width=1, length=None, signed=False, value=None):
+    def __init__(self, name, width=1, length=None, signed=False, value=None, initvalue=None):
         self.name = name
         self.width = width
         self.length = length
         self.signed = signed
         self.value = value
+        self.initvalue = initvalue
 
     def __call__(self, r):
         return Subst(self, r)