Merge branch 'fix_simulation_outputfile' into develop

Author: shtaxxx

examples/simulation_verilator/test_simulation_verilator.py

@@ -2549,19 +2549,17 @@
 int main(int argc, char** argv)
 {
   Verilated::commandArgs(argc, argv);
-  
+
   Top *top = new Top();
 
-#ifdef TRACE  
+#ifdef TRACE
   Verilated::traceEverOn(true);
   VerilatedVcdC* tfp = new VerilatedVcdC;
   top->trace(tfp, 99);
   tfp->open("simulation_verilator.vcd");
 #endif
   top->io_CLK = 0;
-  
   top->io_RST = 0;
-  
 
   // input initialization
 
@@ -2579,8 +2577,8 @@
     // update input
 
     top->eval();
-    
-#ifdef TRACE    
+
+#ifdef TRACE
     tfp->dump(main_time);
 #endif
 
@@ -2592,10 +2590,10 @@
     main_time += TIME_STEP;
   }
 
-#ifdef TRACE    
+#ifdef TRACE
   tfp->close();
 #endif
-  
+
   top->final();
 
   return 0;

tests/simulation/simulator/verilator/simulation_simulator_verilator.py

@@ -30,7 +30,7 @@ def mkLed():
         led.inc()
     )
 
-    seq(
+    seq.If(led < 4)(
         Systask('display', "LED:%d count:%d", led, count)
     )
 
@@ -64,7 +64,7 @@ def mkTest():
     test = mkTest()
 
     sim = simulation.Simulator(test, sim='verilator')
-    rslt = sim.run(sim_time=1000 * 2)
+    rslt = sim.run(sim_time=10000)
     print(rslt)
 
     # sim.view_waveform()

tests/simulation/simulator/verilator/test_simulation_simulator_verilator.py

@@ -143,65 +143,12 @@
 LED:  3 count:        29
 LED:  3 count:        30
 LED:  3 count:        31
-LED:  4 count:         0
-LED:  4 count:         1
-LED:  4 count:         2
-LED:  4 count:         3
-LED:  4 count:         4
-LED:  4 count:         5
-LED:  4 count:         6
-LED:  4 count:         7
-LED:  4 count:         8
-LED:  4 count:         9
-LED:  4 count:        10
-LED:  4 count:        11
-LED:  4 count:        12
-LED:  4 count:        13
-LED:  4 count:        14
-LED:  4 count:        15
-LED:  4 count:        16
-LED:  4 count:        17
-LED:  4 count:        18
-LED:  4 count:        19
-LED:  4 count:        20
-LED:  4 count:        21
-LED:  4 count:        22
-LED:  4 count:        23
-LED:  4 count:        24
-LED:  4 count:        25
-LED:  4 count:        26
-LED:  4 count:        27
-LED:  4 count:        28
-LED:  4 count:        29
-LED:  4 count:        30
-LED:  4 count:        31
-LED:  5 count:         0
-LED:  5 count:         1
-LED:  5 count:         2
-LED:  5 count:         3
-LED:  5 count:         4
-LED:  5 count:         5
-LED:  5 count:         6
-LED:  5 count:         7
-LED:  5 count:         8
-LED:  5 count:         9
-LED:  5 count:        10
-LED:  5 count:        11
-LED:  5 count:        12
-LED:  5 count:        13
-LED:  5 count:        14
-LED:  5 count:        15
-LED:  5 count:        16
-LED:  5 count:        17
-LED:  5 count:        18
-LED:  5 count:        19
-LED:  5 count:        20
 """
 
 
 def test():
     vg.reset()
     test_module = simulation_simulator_verilator.mkTest()
     sim = vg.simulation.Simulator(test_module, sim='verilator')
-    rslt = sim.run(sim_time=1000 * 2)
+    rslt = sim.run(sim_time=10000)
     assert(expected_rslt == rslt)

veriloggen/simulation/verilator_template.cpp

@@ -22,10 +22,10 @@ double sc_time_stamp(){
 int main(int argc, char** argv)
 {
   Verilated::commandArgs(argc, argv);
-  
+
   Top *top = new Top();
 
-#ifdef TRACE  
+#ifdef TRACE
   Verilated::traceEverOn(true);
   VerilatedVcdC* tfp = new VerilatedVcdC;
   top->trace(tfp, 99);
@@ -34,17 +34,17 @@ int main(int argc, char** argv)
 
   {%- for clk in clks.keys() %}
   top->{{ clk }} = 0;
-  {% endfor %}
-  
+  {%- endfor %}
+
   {%- for rst, (period, positive) in rsts.items() %}
   top->{{ rst }} = {% if positive %}0{% else %}1{% endif %};
-  {% endfor %}
+  {%- endfor %}
 
   {%- for init_name, init_val in inits.items() %}
   top->{{ init_name }} = {{ init_val }};
-  {% endfor %}
+  {%- endfor %}
 
-  // input initialization 
+  // input initialization
   {%- for input_name in inputs %}
   top->{{ input_name }} = 0;
   {%- endfor %}
@@ -55,7 +55,7 @@ int main(int argc, char** argv)
       top->{{ clk }} = !top->{{ clk }};
     }
     {%- endfor %}
-    
+
     {%- for rst, (period, positive) in rsts.items() %}
     if(main_time == {{ period }}){
       top->{{ rst }} = {% if positive %}1{% else %}0{% endif %};
@@ -65,14 +65,14 @@ int main(int argc, char** argv)
     }
     {%- endfor %}
 
-    // update input 
+    // update input
     {%- for input_name in inputs %}
     top->{{ input_name }} = 0;
     {%- endfor %}
 
     top->eval();
-    
-#ifdef TRACE    
+
+#ifdef TRACE
     tfp->dump(main_time);
 #endif
 
@@ -84,10 +84,10 @@ int main(int argc, char** argv)
     main_time += TIME_STEP;
   }
 
-#ifdef TRACE    
+#ifdef TRACE
   tfp->close();
 #endif
-  
+
   top->final();
 
   return 0;