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Supports IP-XACT format interrupt signals.
1 parent f95000c commit a8ad160

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2 files changed

+75
-2
lines changed

2 files changed

+75
-2
lines changed

veriloggen/types/componentgen.py

Lines changed: 67 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@ def __init__(self):
3333
self.bus_interfaces = None
3434
self.clk_ports = None
3535
self.rst_ports = None
36+
self.irq_ports = None
3637
self.ext_ports = None
3738
self.ext_params = None
3839

@@ -46,7 +47,7 @@ def __init__(self):
4647
self.dependency_consumer = set()
4748

4849
def generate(self, m, ip_name, bus_interfaces,
49-
clk_ports, rst_ports,
50+
clk_ports, rst_ports, irq_ports,
5051
ext_ports, ext_params,
5152
vendor='user.org', library='user', version='1.0',
5253
description='user description',
@@ -57,6 +58,7 @@ def generate(self, m, ip_name, bus_interfaces,
5758
self.bus_interfaces = bus_interfaces
5859
self.clk_ports = clk_ports
5960
self.rst_ports = rst_ports
61+
self.irq_ports = irq_ports
6062
self.ext_ports = ext_ports
6163
self.ext_params = ext_params
6264

@@ -151,6 +153,9 @@ def mkBusInterfaces(self):
151153
for clk_name, assoc_rsts in self.clk_ports.items():
152154
bus.appendChild(self.mkBusInterfaceClock(clk_name, assoc_rsts))
153155

156+
for irq_name, sensitivity in self.irq_ports.items():
157+
bus.appendChild(self.mkBusInterfaceInterrupt(irq_name, sensitivity))
158+
154159
return bus
155160

156161
def mkBusInterface(self, obj):
@@ -407,6 +412,67 @@ def mkBusParameterPolarity(self, name, polarity):
407412
parameter.appendChild(value)
408413
return parameter
409414

415+
def mkBusInterfaceInterrupt(self, name, sensitivity):
416+
interface = self.doc.createElement('spirit:busInterface')
417+
interface.appendChild(self.mkName(name))
418+
interface.appendChild(self.mkBusTypeInterrupt())
419+
interface.appendChild(self.mkAbstractionTypeInterrupt())
420+
interface.appendChild(self.mkMasterInterrupt())
421+
interface.appendChild(self.mkPortMapsInterrupt(name))
422+
interface.appendChild(self.mkBusParametersInterrupt(name, sensitivity))
423+
return interface
424+
425+
def mkBusTypeInterrupt(self):
426+
bustype = self.doc.createElement('spirit:busType')
427+
self.setAttribute(bustype, 'spirit:vendor', "xilinx.com")
428+
self.setAttribute(bustype, 'spirit:library', "signal")
429+
self.setAttribute(bustype, 'spirit:name', "interrupt")
430+
self.setAttribute(bustype, 'spirit:version', "1.0")
431+
return bustype
432+
433+
def mkAbstractionTypeInterrupt(self):
434+
abstractiontype = self.doc.createElement('spirit:abstractionType')
435+
self.setAttribute(abstractiontype, 'spirit:vendor', "xilinx.com")
436+
self.setAttribute(abstractiontype, 'spirit:library', "signal")
437+
self.setAttribute(abstractiontype, 'spirit:name', "interrupt_rtl")
438+
self.setAttribute(abstractiontype, 'spirit:version', "1.0")
439+
return abstractiontype
440+
441+
def mkMasterInterrupt(self):
442+
master = self.doc.createElement('spirit:master')
443+
return master
444+
445+
def mkPortMapsInterrupt(self, name):
446+
portmaps = self.doc.createElement('spirit:portMaps')
447+
portmaps.appendChild(self.mkPortMapInterrupt(name))
448+
return portmaps
449+
450+
def mkPortMapInterrupt(self, name):
451+
portmap = self.doc.createElement('spirit:portMap')
452+
portmap.appendChild(self.mkLogicalPort('INTERRUPT'))
453+
portmap.appendChild(self.mkPhysicalPortInterrupt(name))
454+
return portmap
455+
456+
def mkPhysicalPortInterrupt(self, name):
457+
physicalport = self.doc.createElement('spirit:physicalPort')
458+
physicalport.appendChild(self.mkName(name))
459+
return physicalport
460+
461+
def mkBusParametersInterrupt(self, name, sensitivity):
462+
parameters = self.doc.createElement('spirit:parameters')
463+
parameters.appendChild(self.mkBusParameterSensitivity(name, sensitivity))
464+
return parameters
465+
466+
def mkBusParameterSensitivity(self, name, sensitivity):
467+
parameter = self.doc.createElement('spirit:parameter')
468+
parameter.appendChild(self.mkName('SENSITIVITY'))
469+
value = self.doc.createElement('spirit:value')
470+
self.setAttribute(value, 'spirit:id', "BUSIFPARAM_VALUE."
471+
+ name.upper() + ".SENSITIVITY")
472+
self.setText(value, sensitivity)
473+
parameter.appendChild(value)
474+
return parameter
475+
410476
def mkAddressSpaces(self):
411477
isempty = True
412478
spaces = self.doc.createElement('spirit:addressSpaces')

veriloggen/types/ipxact.py

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212

1313

1414
def to_ipxact(m, ip_name=None, ip_ver='1.0',
15-
clk_ports=None, rst_ports=None):
15+
clk_ports=None, rst_ports=None, irq_ports=None):
1616

1717
if ip_name is None:
1818
ip_name = m.name
@@ -31,6 +31,12 @@ def to_ipxact(m, ip_name=None, ip_ver='1.0',
3131
if isinstance(rst_ports, (list, tuple)):
3232
rst_ports = OrderedDict(rst_ports)
3333

34+
if irq_ports is None:
35+
irq_ports = {}
36+
37+
if isinstance(irq_ports, (list, tuple)):
38+
irq_ports = OrderedDict(irq_ports)
39+
3440
dirname = ''.join([ip_name, '_v', ip_ver.replace('.', '_'), '/'])
3541

3642
verilogname = ip_name + '.v'
@@ -92,6 +98,7 @@ def to_ipxact(m, ip_name=None, ip_ver='1.0',
9298
bus_interfaces,
9399
clk_ports,
94100
rst_ports,
101+
irq_ports,
95102
ext_ports,
96103
ext_params,
97104
version=ip_ver)

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