source_join_and_run is implemented.

Author: shtaxxx

tests/extension/thread_/stream_reduce_source_join/thread_stream_reduce_source_join.py

@@ -122,7 +122,7 @@ def mkTest(memimg_name=None):
                      params=m.connect_params(led),
                      ports=m.connect_ports(led))
 
-    simulation.setup_waveform(m, uut)
+    # simulation.setup_waveform(m, uut)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
 

tests/extension/thread_/stream_reduce_source_join_and_run/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

tests/extension/thread_/stream_reduce_source_join_and_run/test_thread_stream_reduce_source_join_and_run.py

@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_stream_reduce_source_join_and_run
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_stream_reduce_source_join_and_run.run(filename=None, simtype=simtype,
+                                                        outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')

tests/extension/thread_/stream_reduce_source_join_and_run/thread_stream_reduce_source_join_and_run.py

@@ -0,0 +1,157 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    datawidth = 32
+    addrwidth = 10
+    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
+    ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
+    ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
+
+    strm = vthread.Stream(m, 'mystream', clk, rst)
+    a = strm.source('a')
+    size = strm.constant('size')
+    sum, sum_valid = strm.ReduceAddValid(a, size)
+    strm.sink(sum, 'sum', when=sum_valid, when_name='sum_valid')
+
+    def comp_stream(size, offset):
+        strm.set_source('a', ram_a, offset, size)
+        strm.set_constant('size', size)
+        strm.set_sink('sum', ram_b, offset, 1)
+        strm.run()
+
+        strm.set_source('a', ram_a, offset + size, size + size)
+        strm.set_constant('size', size + size)
+        strm.set_sink('sum', ram_b, offset + 1, 1)
+        strm.source_join_and_run()
+
+        strm.set_source('a', ram_a, offset + size + size + size, size + size + size)
+        strm.set_constant('size', size + size + size)
+        strm.set_sink('sum', ram_b, offset + 2, 1)
+        strm.source_join_and_run()
+
+        strm.source_join()
+        strm.sink_join()
+
+    def comp_sequential(size, offset):
+        sum = 0
+        for i in range(size):
+            a = ram_a.read(i + offset)
+            sum += a
+        ram_b.write(offset, sum)
+
+        sum = 0
+        for i in range(size + size):
+            a = ram_a.read(i + offset + size)
+            sum += a
+        ram_b.write(offset + 1, sum)
+
+        sum = 0
+        for i in range(size + size + size):
+            a = ram_a.read(i + offset + size + size + size)
+            sum += a
+        ram_b.write(offset + 2, sum)
+
+    def check(size, offset_stream, offset_seq):
+        all_ok = True
+        for i in range(size):
+            st = ram_b.read(i + offset_stream)
+            sq = ram_b.read(i + offset_seq)
+            if vthread.verilog.NotEql(st, sq):
+                all_ok = False
+        if all_ok:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+    def comp(size):
+        offset = 0
+        myaxi.dma_read(ram_a, offset, 0, size * 6)
+        comp_stream(size, offset)
+        myaxi.dma_write(ram_b, offset, 1024, 1)
+
+        offset = size
+        myaxi.dma_read(ram_a, offset, 0, size * 6)
+        comp_sequential(size, offset)
+        myaxi.dma_write(ram_b, offset, 1024 * 2, 1)
+
+        check(3, 0, offset)
+
+        vthread.finish()
+
+    th = vthread.Thread(m, 'th_comp', clk, rst, comp)
+    fsm = th.start(32)
+
+    return m
+
+
+def mkTest(memimg_name=None):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
+    memory.connect(ports, 'myaxi')
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    # simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    sim = simulation.Simulator(test, sim=simtype)
+    rslt = sim.run(outputfile=outputfile)
+    lines = rslt.splitlines()
+    if simtype == 'verilator' and lines[-1].startswith('-'):
+        rslt = '\n'.join(lines[:-1])
+    return rslt
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)

veriloggen/thread/stream.py

@@ -47,6 +47,7 @@ class Stream(BaseStream):
                       'run', 'join', 'done',
                       'source_join', 'source_done',
                       'sink_join', 'sink_done',
+                      'source_join_and_run',
                       'enable_dump', 'disable_dump')
     ram_delay = 4
 
@@ -932,19 +933,27 @@ def read_sink(self, fsm, name):
         return var.sink_ram_wdata
 
     def run(self, fsm):
-        # entry point
-        self.fsm._set_index(0)
-
         cond = self._set_flag(fsm)
+
+        self._run(cond)
+
+        fsm.goto_next()
+        fsm.goto_next()
+
+        return 0
+
+    def _run(self, cond):
         add_mux(self.start_flag, cond, 1)
 
-        # after started
-        if self.fsm_synthesized:
-            fsm.goto_next()
-            fsm.goto_next()
-            return
+        if not self.fsm_synthesized:
+            self._synthesize_run()
+            self.fsm_synthesized = True
 
-        self.fsm_synthesized = True
+        return 0
+
+    def _synthesize_run(self):
+        # entry point
+        self.fsm._set_index(0)
 
         start_cond = vtypes.Ands(self.fsm.here, self.start_flag)
 
@@ -1122,9 +1131,6 @@ def run(self, fsm):
 
         self.fsm.goto_init()
 
-        fsm.goto_next()
-        fsm.goto_next()
-
         return 0
 
     def join(self, fsm):
@@ -1150,6 +1156,16 @@ def sink_join(self, fsm):
     def sink_done(self, fsm):
         return vtypes.Not(self.sink_busy)
 
+    def source_join_and_run(self, fsm):
+        cond = vtypes.Ands(fsm.here, vtypes.Not(self.source_busy))
+
+        self._run(cond)
+
+        fsm.If(vtypes.Not(self.source_busy)).goto_next()
+        fsm.goto_next()
+
+        return 0
+
     def enable_dump(self, fsm):
         if not self.dump:
             raise TypeError('dump mode is disabled.')
@@ -1233,7 +1249,7 @@ def _setup_source_ram_dump(self, ram, var, read_enable, read_data):
                           'o' if data_base == 8 else
                           'd' if (data_base == 10 and
                                   (not hasattr(ram, 'point') or ram.point <= 0)) else
-                          #'f' if (data_base == 10 and
+                          # 'f' if (data_base == 10 and
                           #        hasattr(ram, 'point') and ram.point > 0) else
                           'g' if (data_base == 10 and
                                   hasattr(ram, 'point') and ram.point > 0) else
@@ -1242,15 +1258,15 @@ def _setup_source_ram_dump(self, ram, var, read_enable, read_data):
                        '0o' if data_base == 8 else
                        '  ' if data_base == 10 else
                        '0x')
-        #if data_base_char == 'f':
+        # if data_base_char == 'f':
         #    point_len = int(math.ceil(ram.point / math.log(10, 2)))
         #    point_len = max(point_len, 8)
         #    total_len = int(math.ceil(ram.datawidth / math.log(10, 2)))
         #    total_len = max(total_len, point_len)
         #    data_vfmt = ''.join([data_prefix, '%',
         #                         '%d.%d' % (total_len + 1, point_len),
         #                         data_base_char])
-        #else:
+        # else:
         #    data_vfmt = ''.join([data_prefix, '%', data_base_char])
         data_vfmt = ''.join([data_prefix, '%', data_base_char])
 
@@ -1695,7 +1711,7 @@ def _setup_sink_ram_dump(self, ram, var, write_enable):
                           'o' if data_base == 8 else
                           'd' if (data_base == 10 and
                                   (not hasattr(ram, 'point') or ram.point <= 0)) else
-                          #'f' if (data_base == 10 and
+                          # 'f' if (data_base == 10 and
                           #        hasattr(ram, 'point') and ram.point > 0) else
                           'g' if (data_base == 10 and
                                   hasattr(ram, 'point') and ram.point > 0) else
@@ -1704,15 +1720,15 @@ def _setup_sink_ram_dump(self, ram, var, write_enable):
                        '0o' if data_base == 8 else
                        '  ' if data_base == 10 else
                        '0x')
-        #if data_base_char == 'f':
+        # if data_base_char == 'f':
         #    point_len = int(math.ceil(ram.point / math.log(10, 2)))
         #    point_len = max(point_len, 8)
         #    total_len = int(math.ceil(ram.datawidth / math.log(10, 2)))
         #    total_len = max(total_len, point_len)
         #    data_vfmt = ''.join([data_prefix, '%',
         #                         '%d.%d' % (total_len + 1, point_len),
         #                         data_base_char])
-        #else:
+        # else:
         #    data_vfmt = ''.join([data_prefix, '%', data_base_char])
         data_vfmt = ''.join([data_prefix, '%', data_base_char])