flags for write_flag() are flushed when write() is called.

Author: shtaxxx

examples/thread_ipcore/test_thread_ipcore.py

@@ -8,8 +8,7 @@
 
   reg CLK;
   reg RST;
-  reg [16-1:0] sw;
-  wire [16-1:0] led;
+  wire [8-1:0] led;
   reg [32-1:0] saxi_awaddr;
   reg saxi_awvalid;
   wire saxi_awready;
@@ -126,7 +125,6 @@
   (
     .CLK(CLK),
     .RST(RST),
-    .sw(sw),
     .led(led),
     .saxi_awaddr(saxi_awaddr),
     .saxi_awvalid(saxi_awvalid),
@@ -528,8 +526,7 @@
 (
   input CLK,
   input RST,
-  input [16-1:0] sw,
-  output reg [16-1:0] led,
+  output reg [8-1:0] led,
   input [32-1:0] saxi_awaddr,
   input saxi_awvalid,
   output saxi_awready,
@@ -679,22 +676,38 @@
       if((_saxi_register_0 == 1) && (th_blink == 2) && (0 == 3)) begin
         _saxi_register_3 <= 0;
       end 
-      if((th_blink == 10) && (3 == 0)) begin
+      if((th_blink == 3) && (3 == 0)) begin
+        _saxi_register_0 <= 0;
+        _saxi_flag_0 <= 0;
+      end 
+      if((th_blink == 3) && (3 == 1)) begin
+        _saxi_register_1 <= 0;
+        _saxi_flag_1 <= 0;
+      end 
+      if((th_blink == 3) && (3 == 2)) begin
+        _saxi_register_2 <= 0;
+        _saxi_flag_2 <= 0;
+      end 
+      if((th_blink == 3) && (3 == 3)) begin
+        _saxi_register_3 <= 0;
+        _saxi_flag_3 <= 0;
+      end 
+      if((th_blink == 11) && (3 == 0)) begin
         _saxi_register_0 <= 1;
         _saxi_flag_0 <= 1;
         _saxi_resetval_0 <= 0;
       end 
-      if((th_blink == 10) && (3 == 1)) begin
+      if((th_blink == 11) && (3 == 1)) begin
         _saxi_register_1 <= 1;
         _saxi_flag_1 <= 1;
         _saxi_resetval_1 <= 0;
       end 
-      if((th_blink == 10) && (3 == 2)) begin
+      if((th_blink == 11) && (3 == 2)) begin
         _saxi_register_2 <= 1;
         _saxi_flag_2 <= 1;
         _saxi_resetval_2 <= 0;
       end 
-      if((th_blink == 10) && (3 == 3)) begin
+      if((th_blink == 11) && (3 == 3)) begin
         _saxi_register_3 <= 1;
         _saxi_flag_3 <= 1;
         _saxi_resetval_3 <= 0;
@@ -745,6 +758,7 @@
   localparam th_blink_10 = 10;
   localparam th_blink_11 = 11;
   localparam th_blink_12 = 12;
+  localparam th_blink_13 = 13;
 
   always @(posedge CLK) begin
     if(RST) begin
@@ -764,7 +778,7 @@
           if(1) begin
             th_blink <= th_blink_2;
           end else begin
-            th_blink <= th_blink_12;
+            th_blink <= th_blink_13;
           end
         end
         th_blink_2: begin
@@ -773,47 +787,50 @@
           end 
         end
         th_blink_3: begin
-          _th_blink_sleep_1 <= _saxi_register_1;
           th_blink <= th_blink_4;
         end
         th_blink_4: begin
-          _th_blink_size_0 <= _saxi_register_2;
+          _th_blink_sleep_1 <= _saxi_register_1;
           th_blink <= th_blink_5;
         end
         th_blink_5: begin
-          _th_blink_i_2 <= 0;
+          _th_blink_size_0 <= _saxi_register_2;
           th_blink <= th_blink_6;
         end
         th_blink_6: begin
+          _th_blink_i_2 <= 0;
+          th_blink <= th_blink_7;
+        end
+        th_blink_7: begin
           if(_th_blink_i_2 < _th_blink_size_0) begin
-            th_blink <= th_blink_7;
+            th_blink <= th_blink_8;
           end else begin
-            th_blink <= th_blink_10;
+            th_blink <= th_blink_11;
           end
         end
-        th_blink_7: begin
+        th_blink_8: begin
           if(_tmp_9 < _th_blink_sleep_1) begin
             _tmp_9 <= _tmp_9 + 1;
           end 
           if(_tmp_9 >= _th_blink_sleep_1) begin
             _tmp_9 <= 0;
           end 
           if(_tmp_9 >= _th_blink_sleep_1) begin
-            th_blink <= th_blink_8;
+            th_blink <= th_blink_9;
           end 
         end
-        th_blink_8: begin
-          led <= led + 1;
-          th_blink <= th_blink_9;
-        end
         th_blink_9: begin
-          _th_blink_i_2 <= _th_blink_i_2 + 1;
-          th_blink <= th_blink_6;
+          led <= led + 1;
+          th_blink <= th_blink_10;
         end
         th_blink_10: begin
-          th_blink <= th_blink_11;
+          _th_blink_i_2 <= _th_blink_i_2 + 1;
+          th_blink <= th_blink_7;
         end
         th_blink_11: begin
+          th_blink <= th_blink_12;
+        end
+        th_blink_12: begin
           th_blink <= th_blink_1;
         end
       endcase

examples/thread_ipcore/thread_ipcore.py

@@ -17,8 +17,7 @@ def mkLed():
     m = Module('blinkled')
     clk = m.Input('CLK')
     rst = m.Input('RST')
-    sw = m.Input('sw', 16)
-    led = m.OutputReg('led', 16, initval=0)
+    led = m.OutputReg('led', 8, initval=0)
 
     datawidth = 32
     addrwidth = 10
@@ -39,6 +38,8 @@ def blink(size):
         while True:
             # wait start
             saxi.wait_flag(0, value=1, resetvalue=0)
+            # reset done
+            saxi.write(3, 0)
 
             sleep = saxi.read(1)
             size = saxi.read(2)