fixed point with negative point value is supported.

Author: shtaxxx

tests/extension/thread_/stream_fixed/thread_stream_fixed.py

@@ -19,7 +19,7 @@ def mkLed():
 
     datawidth = 32
     addrwidth = 10
-    point = 32
+    point = 4
     myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
     ram_a = vthread.FixedRAM(m, 'ram_a', clk, rst, datawidth, addrwidth,
                              point=point)
@@ -32,14 +32,14 @@ def mkLed():
     a = strm.source('a', point=point)
     b = strm.source('b', point=point)
     const = strm.constant('const', point=point)
-    c = a + b + const
+    c = a * b + const
     strm.sink(c, 'c')
 
     def comp_stream(size, offset):
         strm.set_source('a', ram_a, offset, size)
         strm.set_source('b', ram_b, offset, size)
         strm.set_sink('c', ram_c, offset, size)
-        const = vthread.fixed.FixedConst(0.0, point=point)
+        const = vthread.fixed.FixedConst(1, point=point)
         strm.set_constant('const', const)
         strm.run()
         strm.join()
@@ -48,10 +48,10 @@ def comp_sequential(size, offset):
         for i in range(size):
             a = ram_a.read(i + offset)
             b = ram_b.read(i + offset)
-            const = vthread.fixed.FixedConst(0.0, point=point)
-            c = a + b + const
+            const = vthread.fixed.FixedConst(1, point=point)
+            c = a * b + const
             ram_c.write(i + offset, c)
-            #print('a = %f, b = %f, const = %f, c =  %f' % (a, b, const, c))
+            print('a = %10g, b = %10g, const = %10g, c =  %10g' % (a, b, const, c))
 
     def check(size, offset_stream, offset_seq):
         all_ok = True

tests/extension/thread_/stream_fixed_neg_point/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

tests/extension/thread_/stream_fixed_neg_point/test_thread_stream_fixed_neg_point.py

@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_stream_fixed_neg_point
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_stream_fixed_neg_point.run(filename=None, simtype=simtype,
+                                             outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')

tests/extension/thread_/stream_fixed_neg_point/thread_stream_fixed_neg_point.py

@@ -0,0 +1,148 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    datawidth = 32
+    addrwidth = 10
+    point = -4
+    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
+    ram_a = vthread.FixedRAM(m, 'ram_a', clk, rst, datawidth, addrwidth,
+                             point=point)
+    ram_b = vthread.FixedRAM(m, 'ram_b', clk, rst, datawidth, addrwidth,
+                             point=point)
+    ram_c = vthread.FixedRAM(m, 'ram_c', clk, rst, datawidth, addrwidth,
+                             point=point)
+
+    strm = vthread.Stream(m, 'mystream', clk, rst, dump=True)
+    a = strm.source('a', point=point)
+    b = strm.source('b', point=point)
+    const = strm.constant('const', point=point)
+    c = a * b + const
+    strm.sink(c, 'c')
+
+    def comp_stream(size, offset):
+        strm.set_source('a', ram_a, offset, size)
+        strm.set_source('b', ram_b, offset, size)
+        strm.set_sink('c', ram_c, offset, size)
+        const = vthread.fixed.FixedConst(32, point=point)
+        strm.set_constant('const', const)
+        strm.run()
+        strm.join()
+
+    def comp_sequential(size, offset):
+        for i in range(size):
+            a = ram_a.read(i + offset)
+            b = ram_b.read(i + offset)
+            const = vthread.fixed.FixedConst(32, point=point)
+            c = a * b + const
+            ram_c.write(i + offset, c)
+            print('a = %10g, b = %10g, const = %10g, c =  %10g' % (a, b, const, c))
+
+    def check(size, offset_stream, offset_seq):
+        all_ok = True
+        for i in range(size):
+            st = ram_c.read(i + offset_stream)
+            sq = ram_c.read(i + offset_seq)
+            if vthread.verilog.NotEql(st, sq):
+                all_ok = False
+        if all_ok:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+    def comp(size):
+        # stream
+        offset = 0
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        comp_stream(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024, size)
+
+        # sequential
+        offset = size
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        comp_sequential(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024 * 2, size)
+
+        # verification
+        check(size, 0, offset)
+
+        vthread.finish()
+
+    th = vthread.Thread(m, 'th_comp', clk, rst, comp)
+    fsm = th.start(32)
+
+    return m
+
+
+def mkTest(memimg_name=None):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
+    memory.connect(ports, 'myaxi')
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    #simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    sim = simulation.Simulator(test, sim=simtype)
+    rslt = sim.run(outputfile=outputfile)
+    lines = rslt.splitlines()
+    if simtype == 'verilator' and lines[-1].startswith('-'):
+        rslt = '\n'.join(lines[:-1])
+    return rslt
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)

veriloggen/stream/stream.py

@@ -329,24 +329,25 @@ def get_name(obj):
                     self.dump_base)
             base_char = ('b' if base == 2 else
                          'o' if base == 8 else
-                         'd' if base == 10 and input_var.point == 0 else
-                         #'f' if base == 10 and input_var.point > 0 else
+                         'd' if base == 10 and input_var.point <= 0 else
+                         # 'f' if base == 10 and input_var.point > 0 else
                          'g' if base == 10 and input_var.point > 0 else
                          'x')
             prefix = ('0b' if base == 2 else
                       '0o' if base == 8 else
                       '  ' if base == 10 else
                       '0x')
 
-            #if base_char == 'f':
+            # if base_char == 'f':
             #    point_length = int(math.ceil(input_var.point / math.log(base, 2)))
             #    point_length = max(point_length, 8)
             #    fmt_list = [prefix, '%',
             #                '%d.%d' % (longest_var_len + 1, point_length), base_char]
-            if base_char == 'g':
-                fmt_list = [prefix, '%', base_char]
-            else:
-                fmt_list = [prefix, '%', '%d' % (longest_var_len + 1), base_char]
+            # if base_char == 'g':
+            #    fmt_list = [prefix, '%', base_char]
+            # else:
+            #    fmt_list = [prefix, '%', '%d' % (longest_var_len + 1), base_char]
+            fmt_list = [prefix, '%', '%d' % (longest_var_len + 1), base_char]
 
             if input_var not in all_vars:
                 fmt_list.append(' (unused)')
@@ -359,24 +360,25 @@ def get_name(obj):
                     self.dump_base)
             base_char = ('b' if base == 2 else
                          'o' if base == 8 else
-                         'd' if base == 10 and output_var.point == 0 else
-                         #'f' if base == 10 and output_var.point > 0 else
+                         'd' if base == 10 and output_var.point <= 0 else
+                         # 'f' if base == 10 and output_var.point > 0 else
                          'g' if base == 10 and output_var.point > 0 else
                          'x')
             prefix = ('0b' if base == 2 else
                       '0o' if base == 8 else
                       '  ' if base == 10 else
                       '0x')
 
-            #if base_char == 'f':
+            # if base_char == 'f':
             #    point_length = int(math.ceil(output_var.point / math.log(base, 2)))
             #    point_length = max(point_length, 8)
             #    fmt_list = [prefix, '%',
             #                '%d.%d' % (longest_var_len + 1, point_length), base_char]
-            if base_char == 'g':
-                fmt_list = [prefix, '%', base_char]
-            else:
-                fmt_list = [prefix, '%', '%d' % (longest_var_len + 1), base_char]
+            # if base_char == 'g':
+            #    fmt_list = [prefix, '%', base_char]
+            # else:
+            #    fmt_list = [prefix, '%', '%d' % (longest_var_len + 1), base_char]
+            fmt_list = [prefix, '%', '%d' % (longest_var_len + 1), base_char]
 
             if output_var not in all_vars:
                 fmt_list.append(' (unused)')
@@ -391,24 +393,25 @@ def get_name(obj):
                     self.dump_base)
             base_char = ('b' if base == 2 else
                          'o' if base == 8 else
-                         'd' if base == 10 and var.point == 0 else
-                         #'f' if base == 10 and var.point > 0 else
+                         'd' if base == 10 and var.point <= 0 else
+                         # 'f' if base == 10 and var.point > 0 else
                          'g' if base == 10 and var.point > 0 else
                          'x')
             prefix = ('0b' if base == 2 else
                       '0o' if base == 8 else
                       '  ' if base == 10 else
                       '0x')
 
-            #if base_char == 'f':
+            # if base_char == 'f':
             #    point_length = int(math.ceil(var.point / math.log(base, 2)))
             #    point_length = max(point_length, 8)
             #    fmt_list = [prefix, '%',
             #                '%d.%d' % (longest_var_len + 1, point_length), base_char]
-            if base_char == 'g':
-                fmt_list = [prefix, '%', base_char]
-            else:
-                fmt_list = [prefix, '%', '%d' % (longest_var_len + 1), base_char]
+            # if base_char == 'g':
+            #    fmt_list = [prefix, '%', base_char]
+            # else:
+            #    fmt_list = [prefix, '%', '%d' % (longest_var_len + 1), base_char]
+            fmt_list = [prefix, '%', '%d' % (longest_var_len + 1), base_char]
 
             var.dump_fmt = ''.join(fmt_list)
 
@@ -437,11 +440,13 @@ def get_name(obj):
             enables.append(enable)
             age = seq.Prev(self.dump_step, stage) - 1
 
-            if input_var.point == 0:
-                sig_data = input_var.sig_data
-            else:
+            if input_var.point > 0:
                 sig_data = vtypes.Div(vtypes.SystemTask('itor', input_var.sig_data),
                                       1.0 * (2 ** input_var.point))
+            elif input_var.point < 0:
+                sig_data = vtypes.Times(input_var.sig_data, 2 ** -input_var.point)
+            else:
+                sig_data = input_var.sig_data
 
             seq.If(enable, vtypes.Not(self.dump_mask))(
                 vtypes.Display(fmt, self.dump_step, stage, age, sig_data)
@@ -470,11 +475,13 @@ def get_name(obj):
             enables.append(enable)
             age = seq.Prev(self.dump_step, stage) - 1
 
-            if var.point == 0:
-                sig_data = var.sig_data
-            else:
+            if var.point > 0:
                 sig_data = vtypes.Div(vtypes.SystemTask('itor', var.sig_data),
                                       1.0 * (2 ** var.point))
+            elif var.point < 0:
+                sig_data = vtypes.Times(var.sig_data, 2 ** -var.point)
+            else:
+                sig_data = var.sig_data
 
             seq.If(enable, vtypes.Not(self.dump_mask))(
                 vtypes.Display(fmt, self.dump_step, stage, age, sig_data)
@@ -504,11 +511,13 @@ def get_name(obj):
             enables.append(enable)
             age = seq.Prev(self.dump_step, stage) - 1
 
-            if output_var.point == 0:
-                sig_data = output_var.output_sig_data
-            else:
+            if output_var.point > 0:
                 sig_data = vtypes.Div(vtypes.SystemTask('itor', output_var.output_sig_data),
                                       1.0 * (2 ** output_var.point))
+            elif output_var.point < 0:
+                sig_data = vtypes.Times(output_var.output_sig_data, 2 ** -output_var.point)
+            else:
+                sig_data = output_var.output_sig_data
 
             seq.If(enable, vtypes.Not(self.dump_mask))(
                 vtypes.Display(fmt, self.dump_step, stage, age, sig_data)