Corrected the argument in some test cases.

shtaxxx · shtaxxx · commit a04b4a974be4 · 2022-04-03T13:25:33.000+09:00
diff --git a/tests/extension/thread_/axi_dma_long_wide/thread_axi_dma_long_wide.py b/tests/extension/thread_/axi_dma_long_wide/thread_axi_dma_long_wide.py
@@ -108,7 +108,8 @@ def mkTest(memimg_name=None, memory_datawidth=128):
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth,
+                                memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
diff --git a/tests/extension/thread_/axi_dma_multiram/thread_axi_dma_multiram.py b/tests/extension/thread_/axi_dma_multiram/thread_axi_dma_multiram.py
@@ -196,7 +196,8 @@ def mkTest(memimg_name=None, memory_datawidth=128):
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth,
+                                memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
diff --git a/tests/extension/thread_/axi_dma_wide/thread_axi_dma_wide.py b/tests/extension/thread_/axi_dma_wide/thread_axi_dma_wide.py
@@ -111,7 +111,8 @@ def mkTest(memimg_name=None, memory_datawidth=128):
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth,
+                                memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
diff --git a/tests/extension/thread_/axi_dma_wide_unaligned/thread_axi_dma_wide_unaligned.py b/tests/extension/thread_/axi_dma_wide_unaligned/thread_axi_dma_wide_unaligned.py
@@ -112,7 +112,8 @@ def mkTest(memimg_name=None, memory_datawidth=128):
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth,
+                                memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
diff --git a/tests/extension/thread_/multibank_nested_ram_dma/thread_multibank_nested_ram_dma.py b/tests/extension/thread_/multibank_nested_ram_dma/thread_multibank_nested_ram_dma.py
@@ -129,7 +129,8 @@ def mkTest(memimg_name=None, memory_datawidth=128):
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth,
+                                memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
diff --git a/tests/extension/thread_/multibank_nested_ram_dma_block/thread_multibank_nested_ram_dma_block.py b/tests/extension/thread_/multibank_nested_ram_dma_block/thread_multibank_nested_ram_dma_block.py
@@ -174,7 +174,8 @@ def mkTest(memimg_name=None, memory_datawidth=128):
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth,
+                                memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
diff --git a/tests/extension/thread_/multibank_nested_ram_dma_block_non_poweroftwo/thread_multibank_nested_ram_dma_block_non_poweroftwo.py b/tests/extension/thread_/multibank_nested_ram_dma_block_non_poweroftwo/thread_multibank_nested_ram_dma_block_non_poweroftwo.py
@@ -174,7 +174,8 @@ def mkTest(memimg_name=None, memory_datawidth=128):
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth,
+                                memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
diff --git a/tests/extension/thread_/multibank_ram_dma_block/thread_multibank_ram_dma_block.py b/tests/extension/thread_/multibank_ram_dma_block/thread_multibank_ram_dma_block.py
@@ -175,7 +175,8 @@ def mkTest(memimg_name=None, memory_datawidth=32):
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth,
+                                memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
diff --git a/tests/extension/thread_/multibank_ram_dma_block_non_poweroftwo/thread_multibank_ram_dma_block_non_poweroftwo.py b/tests/extension/thread_/multibank_ram_dma_block_non_poweroftwo/thread_multibank_ram_dma_block_non_poweroftwo.py
@@ -175,7 +175,8 @@ def mkTest(memimg_name=None, memory_datawidth=32):
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth,
+                                memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
diff --git a/tests/extension/thread_/multibank_ram_dma_packed/thread_multibank_ram_dma_packed.py b/tests/extension/thread_/multibank_ram_dma_packed/thread_multibank_ram_dma_packed.py
@@ -127,7 +127,8 @@ def mkTest(memimg_name=None, memory_datawidth=128):
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth,
+                                memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
diff --git a/tests/extension/thread_/multibank_ram_dma_packed_long/thread_multibank_ram_dma_packed_long.py b/tests/extension/thread_/multibank_ram_dma_packed_long/thread_multibank_ram_dma_packed_long.py
@@ -123,7 +123,8 @@ def mkTest(memimg_name=None, memory_datawidth=128):
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth,
+                                memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
diff --git a/tests/extension/thread_/multibank_ram_dma_packed_narrow/thread_multibank_ram_dma_packed_narrow.py b/tests/extension/thread_/multibank_ram_dma_packed_narrow/thread_multibank_ram_dma_packed_narrow.py
@@ -127,7 +127,8 @@ def mkTest(memimg_name=None, memory_datawidth=32):
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth,
+                                memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
diff --git a/tests/extension/thread_/multibank_ram_dma_packed_wide/thread_multibank_ram_dma_packed_wide.py b/tests/extension/thread_/multibank_ram_dma_packed_wide/thread_multibank_ram_dma_packed_wide.py
@@ -125,7 +125,8 @@ def mkTest(memimg_name=None, memory_datawidth=256):
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth,
+                                memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
diff --git a/tests/extension/thread_/multibank_ram_dma_wide/thread_multibank_ram_dma_wide.py b/tests/extension/thread_/multibank_ram_dma_wide/thread_multibank_ram_dma_wide.py
@@ -114,7 +114,8 @@ def mkTest(memimg_name=None, memory_datawidth=128):
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth,
+                                memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
diff --git a/tests/extension/thread_/stream_multibank/thread_stream_multibank.py b/tests/extension/thread_/stream_multibank/thread_stream_multibank.py
@@ -108,7 +108,8 @@ def mkTest(memimg_name=None, memory_datawidth=128):
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth,
+                                memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
diff --git a/tests/extension/thread_/stream_multibank_nested/thread_stream_multibank_nested.py b/tests/extension/thread_/stream_multibank_nested/thread_stream_multibank_nested.py
@@ -114,7 +114,8 @@ def mkTest(memimg_name=None, memory_datawidth=128):
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth,
+                                memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
diff --git a/tests/extension/thread_/to_multibank_ram/thread_to_multibank_ram.py b/tests/extension/thread_/to_multibank_ram/thread_to_multibank_ram.py
@@ -116,7 +116,8 @@ def mkTest(memimg_name=None, memory_datawidth=128):
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memory_datawidth,
+                                memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
