Merge branch 'feature_stream_split' into develop

shtaxxx · shtaxxx · commit 9f11af99c3b5 · 2019-05-03T12:46:53.000+09:00
diff --git a/tests/extension/thread_/stream_split/Makefile b/tests/extension/thread_/stream_split/Makefile
@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd
diff --git a/tests/extension/thread_/stream_split/test_thread_stream_split.py b/tests/extension/thread_/stream_split/test_thread_stream_split.py
@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_stream_split
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_stream_split.run(filename=None, simtype=simtype,
+                                   outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')
diff --git a/tests/extension/thread_/stream_split/thread_stream_split.py b/tests/extension/thread_/stream_split/thread_stream_split.py
@@ -0,0 +1,154 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    datawidth = 32
+    addrwidth = 10
+    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
+    ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
+    ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
+    ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
+
+    strm = vthread.Stream(m, 'mystream', clk, rst)
+    a = strm.source('a')  # 32-bit
+    b = strm.source('b')  # 32-bit
+
+    a_list = strm.Split(a, width=8, point=0, signed=True)  # 8-bit, (32/8=4)-word
+    ## a_list : [a[31:24], a[23:16], a[15:8], a[7:0]]
+
+    b_list = strm.Split(b, width=8, point=0, signed=True)  # 8-bit, (32/8=4)-word
+    ## b_list : [b[31:24], b[23:16], b[15:8], b[7:0]]
+
+    c_list = [ai + bi for ai, bi in zip(a_list, b_list)]  # SIMD-like addition
+    c = strm.Cat(*c_list)  # 32-bit
+
+    strm.sink(c, 'c')
+
+    def comp_stream(size, offset):
+        strm.set_source('a', ram_a, offset, size)
+        strm.set_source('b', ram_b, offset, size)
+        strm.set_sink('c', ram_c, offset, size)
+        strm.run()
+        strm.join()
+
+    def comp_sequential(size, offset):
+        for i in range(size):
+            a = ram_a.read(i + offset)
+            b = ram_b.read(i + offset)
+            sum = 0
+            for j in range(0, 32, 8):
+                aj = (a >> j) & 0xff
+                bj = (b >> j) & 0xff
+                cj = (aj + bj) & 0xff
+                sum = (cj << j) | sum
+            ram_c.write(i + offset, sum)
+
+    def check(size, offset_stream, offset_seq):
+        all_ok = True
+        for i in range(size):
+            st = ram_c.read(i + offset_stream)
+            sq = ram_c.read(i + offset_seq)
+            if vthread.verilog.NotEql(st, sq):
+                all_ok = False
+                print(i, st, sq)
+        if all_ok:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+    def comp(size):
+        # stream
+        offset = 0
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        comp_stream(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024, size)
+
+        # sequential
+        offset = size
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        comp_sequential(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024 * 2, size)
+
+        # verification
+        check(size, 0, offset)
+
+        vthread.finish()
+
+    th = vthread.Thread(m, 'th_comp', clk, rst, comp)
+    fsm = th.start(32)
+
+    return m
+
+
+def mkTest(memimg_name=None):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
+    memory.connect(ports, 'myaxi')
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    #simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    sim = simulation.Simulator(test, sim=simtype)
+    rslt = sim.run(outputfile=outputfile)
+    lines = rslt.splitlines()
+    if simtype == 'verilator' and lines[-1].startswith('-'):
+        rslt = '\n'.join(lines[:-1])
+    return rslt
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)
diff --git a/veriloggen/stream/stypes.py b/veriloggen/stream/stypes.py
@@ -1497,6 +1497,83 @@ def eval(self):
         return Slice(var, msb, lsb)
 
 
+def Split(data, width=None, point=None, signed=None, num_chunks=None):
+    """
+    Split the given data into multiple chunks
+
+    Parameters
+    ----------
+    data : _Numeric
+        Input data
+
+    width : int
+        Data width of separated chunks (default: same as input data)
+
+    point : int
+        Fixed-point position of separated chunks (default: same as input data)
+
+    signed : bool
+        Sign (default: same as input data)
+
+    num_chunks: int
+        The number of separated chunks (default: (input data width) / width)
+
+    Returns
+    -------
+    chunks : list
+        A list of separated chunks
+
+        For the consistency with Cat operator, the order of chunks is higher-bit first.
+        If data is a 32-bit value, and width is 8, returned list of chunks will be
+            chunks = [data[31:24], data[23:16], data[15:8], data[7:0]]
+    """
+
+    data = _to_constant(data)
+
+    if width is None and num_chunks is None:
+        raise ValueError('width or num_chunks must be specified.')
+
+    if width is not None and num_chunks is not None:
+        raise ValueError('Either of width or num_chunks must be specified.')
+
+    if width is None:
+        width = int(ceil(data.bit_length() / num_chunks))
+    elif num_chunks is None:
+        num_chunks = int(ceil(data.bit_length() / width))
+
+    if point is None:
+        point = data.get_point()
+
+    if signed is None:
+        signed = data.get_signed()
+
+    total_width = width * num_chunks
+    ret = []
+    for i in range(0, total_width, width):
+        if i + width > data.bit_length():
+            if signed:
+                sign = data[-1]
+                sign.latency = 0
+                pad = Repeat(sign, total_width - data.bit_length())
+                pad.latency = 0
+            else:
+                pad = Int(0, signed=False)
+                pad.width = total_width - data.bit_length()
+
+            slc = Slice(data, data.bit_length() - 1, i)
+            slc.latency = 0
+            v = Cat(pad, slc)
+            v.latency = 0
+        else:
+            v = Slice(data, i + width - 1, i)
+            v.latency = 0
+
+        ret.append(Cast(v, width, point, signed))
+
+    ret.reverse()
+    return ret
+
+
 class Cat(_SpecialOperator):
 
     def __init__(self, *vars):
