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write method for FromExtern
1 parent 976b7bf commit 9e749a2

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2 files changed

+18
-9
lines changed

2 files changed

+18
-9
lines changed

tests/extension/thread_/stream_extern/thread_stream_extern.py

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -27,27 +27,29 @@ def mkLed():
2727

2828
a = strm.source('a')
2929

30-
# to extern
30+
# to/from extern
3131
extout = strm.ToExtern(a)
3232
extin = strm.FromExtern(extout, latency=1)
3333

34-
# from extern
35-
b = a + extin + 1
34+
b = extin + 1000
3635

3736
strm.sink(b, 'b')
3837

3938
def comp_stream(size, offset):
4039
strm.set_source('a', ram_a, offset, size)
4140
strm.set_sink('b', ram_b, offset, size)
41+
# reset FromExtern value
42+
extin.write(0)
4243
strm.run()
4344
strm.join()
4445

4546
def comp_sequential(size, offset):
47+
extin = 0
4648
for i in range(size):
4749
a = ram_a.read(i + offset)
4850
extout = a
49-
extin = extout + 100
50-
b = a + extin + 1
51+
extin += extout
52+
b = extin + 1000
5153
ram_b.write(i + offset, b)
5254

5355
def check(size, offset_stream, offset_seq):
@@ -83,10 +85,9 @@ def comp(size):
8385
th = vthread.Thread(m, 'th_comp', clk, rst, comp)
8486
fsm = th.start(32)
8587

86-
# extern behavior in RTL
87-
ext_seq = Seq(m, 'ext_seq', clk, rst)
88-
ext_seq.If(extout.valid)(
89-
extin.data(extout.data + 100)
88+
# extern behavior in RTL (accumulator)
89+
extin.seq.If(extout.valid)(
90+
extin.data(extin.data + extout.data)
9091
)
9192

9293
return m

veriloggen/stream/stypes.py

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3135,6 +3135,7 @@ def _implement(self, m, seq, svalid=None, senable=None):
31353135

31363136

31373137
class FromExtern(_UnaryOperator):
3138+
__intrinsics__ = ('write')
31383139
latency = 1
31393140

31403141
def __init__(self, right, width=None, point=None, signed=True, latency=1):
@@ -3170,6 +3171,13 @@ def _implement(self, m, seq, svalid=None, senable=None):
31703171
data = m.Reg(self.name('data'), width, initval=0, signed=signed)
31713172
self.sig_data = data
31723173

3174+
def write(self, fsm, value):
3175+
cond = fsm.here
3176+
3177+
self.seq.If(cond)(
3178+
self.sig_data(value)
3179+
)
3180+
31733181

31743182
class Reg(_SpecialOperator):
31753183
__intrinsics__ = ('write')

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