System task is now supported.

Author: shtaxxx

sample/test/function/led.py

@@ -42,8 +42,8 @@ def mkLed():
             If(count == 1023)(
                 count(0)
             ).Else(
-                count( FunctionCall(inc.name, count, 1) )
-                #count( inc.call(count, 1) )
+                #count( FunctionCall(inc.name, count, 1) + 1 - 1 )
+                count( inc.call(count, 1) + 1 - 1 )
             )
         ))
 

sample/test/function/test_led.py

@@ -39,7 +39,7 @@
       if(count == 1023) begin
         count <= 0;
       end else begin
-        count <= inc(count, 1);
+        count <= inc(count, 1) + 1 - 1;
       end
     end 
   end 

sample/test/read_verilog/Makefile

@@ -1,30 +1,7 @@
-TARGET=led.py
-TEST=test_led.py
-ARGS=
-
-PYTHON=python3
-#PYTHON=python
-#OPT=-m pdb
-#OPT=-m cProfile -s time
-#OPT=-m cProfile -o profile.rslt
-
-.PHONY: all
-all: test
-
-.PHONY: run
-run:
-	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+.PHONY: clean
+clean:
+	find . -maxdepth 1 -type d |grep "./" | xargs -I {} make clean -C {} 
 
 .PHONY: test
 test:
-	$(PYTHON) -m pytest -vv $(TEST)
-
-.PHONY: check
-check:
-	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
-	iverilog -tnull -Wall tmp.v
-	rm -f tmp.v
-
-.PHONY: clean
-clean:
-	rm -rf *.pyc __pycache__ parsetab.py *.out
+	find . -maxdepth 1 -type d |grep "./" | xargs -I {} make test -C {} 

sample/test/read_verilog/module/led.py

@@ -18,8 +18,9 @@ def mkTop():
 
     params = ( width, )
     ports = ( clk, rst, led )
-    
-    m.Instance(mkLed(), 'inst_blinkled', params, ports)
+
+    led = mkLed()
+    m.Instance(led, 'inst_blinkled', params, ports)
 
     return m
 

sample/test/systemtask/Makefile

@@ -0,0 +1,30 @@
+TARGET=led.py
+TEST=test_led.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv $(TEST)
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out

sample/test/systemtask/led.py

@@ -0,0 +1,40 @@
+import sys
+import os
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', width)
+    count = m.Reg('count', 32)
+
+    m.Always(Posedge(clk))(
+        If(rst)(
+            count(0)
+        ).Else(
+            If(count == 1023)(
+                count(0)
+            ).Else(
+                count(count + 1)
+            )
+        ))
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            led(0)
+        ).Else(
+            If(count == 1024 - 1)(
+                led(led + 1),
+                SystemTask('display', 'led:%x', led)
+            )
+        ))
+    
+    return m
+
+if __name__ == '__main__':
+    led = mkLed()
+    # led.to_verilog(filename='tmp.v')
+    verilog = led.to_verilog()
+    print(verilog)

sample/test/systemtask/test_led.py

@@ -0,0 +1,49 @@
+import led
+
+expected_verilog = """
+module blinkled #
+  ( 
+   parameter WIDTH = 8
+  )
+  ( 
+   input CLK, 
+   input RST,
+   output reg [WIDTH-1:0] LED
+  );
+  reg [32-1:0] count;
+  always @(posedge CLK) begin
+    if(RST) begin
+      count <= 0;
+    end else begin
+      if(count == 1023) begin
+        count <= 0;
+      end else begin
+        count <= count + 1;
+      end
+    end
+  end
+  always @(posedge CLK) begin
+    if(RST) begin
+      LED <= 0;
+    end else begin
+      if(count == 1023) begin
+        LED <= LED + 1;
+        $display("led:%x", LED);
+      end 
+    end
+  end
+endmodule
+"""
+
+def test_led():
+    led_module = led.mkLed()
+    led_code = led_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(led_code == expected_code)

sample/test/systemtask/veriloggen

@@ -0,0 +1 @@
+../../../veriloggen

veriloggen/function.py

@@ -46,7 +46,7 @@ def next(self, r):
     def call(self, *args):
         return FunctionCall(self.name, *args)
 
-class FunctionCall(vtypes.VeriloggenNode):
+class FunctionCall(vtypes._Numeric):
     def __init__(self, name, *args):
         self.name = name
         self.args = tuple(args)

veriloggen/module.py

@@ -214,6 +214,28 @@ def add_object(self, obj):
             self.initial.append(obj)
             return
 
+        if isinstance(obj, GenerateFor):
+            if obj.scope is None:
+                if None not in self.generate: self.generate[None] = []
+                self.generate[None].append(obj)
+                return
+            self.generate[obj.scope] = obj
+            return
+
+        if isinstance(obj, GenerateIf):
+            if obj.true_scope is None:
+                if None not in self.generate: self.generate[None] = []
+                self.generate[None].append(obj)
+                return
+            self.generate[obj.true_scope] = obj
+            return
+
+        if isinstance(obj, Instance):
+            self.instance[obj.name] = obj
+            if isinstance(obj.module, Module):
+                self.submodule[obj.module.name] = obj.module
+            return
+
         raise TypeError("Object type '%s' is not supported." % str(type(obj)))
 
     #---------------------------------------------------------------------------
@@ -278,7 +300,7 @@ def to_verilog(self, filename=None):
         return to_verilog.write_verilog(self, filename)
 
 #-------------------------------------------------------------------------------
-class StubModule(Module):
+class StubModule(vtypes.VeriloggenNode):
     """ Verilog Module class """
     def __init__(self, name=None):
         self.name = name if name is not None else self.__class__.__name__
@@ -303,7 +325,7 @@ def __init__(self, module, instname, params, ports):
             self.ports = [ (None, p) for p in ports ]
 
     def type_check_module(self, module):
-        if not isinstance(module, Module):
+        if not isinstance(module, (Module, StubModule)):
             raise TypeError("module of Instance must be Module or StubModule, not %s" %
                             type(module))