PyHDI
diff --git a/‎tests/verilog/read_verilog_/Makefile‎ renamed to ‎tests/verilog/from_verilog_/Makefile‎ b/‎tests/verilog/read_verilog_/Makefile‎ renamed to ‎tests/verilog/from_verilog_/Makefile‎
diff --git a/‎tests/verilog/read_verilog_/branchpredunit/Makefile‎ renamed to ‎tests/verilog/from_verilog_/branchpredunit/Makefile‎ b/‎tests/verilog/read_verilog_/branchpredunit/Makefile‎ renamed to ‎tests/verilog/from_verilog_/branchpredunit/Makefile‎
diff --git a/‎tests/verilog/read_verilog_/branchpredunit/branch.v‎ renamed to ‎tests/verilog/from_verilog_/branchpredunit/branch.v‎ b/‎tests/verilog/read_verilog_/branchpredunit/branch.v‎ renamed to ‎tests/verilog/from_verilog_/branchpredunit/branch.v‎
diff --git a/‎tests/verilog/read_verilog_/branchpredunit/read_verilog_branchpredunit.py‎ renamed to ‎tests/verilog/from_verilog_/branchpredunit/from_verilog_branchpredunit.py‎ b/‎tests/verilog/read_verilog_/branchpredunit/read_verilog_branchpredunit.py‎ renamed to ‎tests/verilog/from_verilog_/branchpredunit/from_verilog_branchpredunit.py‎
diff --git a/‎tests/verilog/read_verilog_/branchpredunit/test_read_verilog_branchpredunit.py‎ renamed to ‎tests/verilog/from_verilog_/branchpredunit/test_from_verilog_branchpredunit.py‎
Lines changed: 2 additions & 2 deletions b/‎tests/verilog/read_verilog_/branchpredunit/test_read_verilog_branchpredunit.py‎ renamed to ‎tests/verilog/from_verilog_/branchpredunit/test_from_verilog_branchpredunit.py‎
Lines changed: 2 additions & 2 deletions
diff --git a/‎tests/verilog/read_verilog_/module/Makefile‎ renamed to ‎tests/verilog/from_verilog_/module/Makefile‎ b/‎tests/verilog/read_verilog_/module/Makefile‎ renamed to ‎tests/verilog/from_verilog_/module/Makefile‎
diff --git a/‎tests/verilog/read_verilog_/module/read_verilog_module.py‎ renamed to ‎tests/verilog/from_verilog_/module/from_verilog_module.py‎ b/‎tests/verilog/read_verilog_/module/read_verilog_module.py‎ renamed to ‎tests/verilog/from_verilog_/module/from_verilog_module.py‎
diff --git a/‎tests/verilog/read_verilog_/module/led.v‎ renamed to ‎tests/verilog/from_verilog_/module/led.v‎ b/‎tests/verilog/read_verilog_/module/led.v‎ renamed to ‎tests/verilog/from_verilog_/module/led.v‎
diff --git a/‎tests/verilog/read_verilog_/module/test_read_verilog_module.py‎ renamed to ‎tests/verilog/from_verilog_/module/test_from_verilog_module.py‎
Lines changed: 2 additions & 2 deletions b/‎tests/verilog/read_verilog_/module/test_read_verilog_module.py‎ renamed to ‎tests/verilog/from_verilog_/module/test_from_verilog_module.py‎
Lines changed: 2 additions & 2 deletions
diff --git a/‎tests/verilog/read_verilog_/module_generate/Makefile‎ renamed to ‎tests/verilog/from_verilog_/module_generate/Makefile‎ b/‎tests/verilog/read_verilog_/module_generate/Makefile‎ renamed to ‎tests/verilog/from_verilog_/module_generate/Makefile‎
@@ -1,7 +1,7 @@
 from __future__ import absolute_import
 from __future__ import print_function
 import veriloggen
-import read_verilog_branchpredunit
+import from_verilog_branchpredunit
 
 expected_verilog = """
 `default_nettype none
@@ -536,7 +536,7 @@
 
 def test():
     veriloggen.reset()
-    test_modules = read_verilog_branchpredunit.mkMips()
+    test_modules = from_verilog_branchpredunit.mkMips()
     code = ''.join([ m.to_verilog() for m in test_modules.values() if not m.used ])
 
     from pyverilog.vparser.parser import parse
 
@@ -1,7 +1,7 @@
 from __future__ import absolute_import
 from __future__ import print_function
 import veriloggen
-import read_verilog_module
+import from_verilog_module
 
 expected_verilog = """
 module top #
@@ -60,7 +60,7 @@
 
 def test():
     veriloggen.reset()
-    test_module = read_verilog_module.mkTop()
+    test_module = from_verilog_module.mkTop()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser